0.15-μm-Gate InAlAs/InGaAs/InP E-HEMTs utilizing Ir/Ti/Pt/Au gate structure

Seiyon Kim, Ilesanmi Adesida

Research output: Contribution to journalArticle

13 Citations (Scopus)

Abstract

High-current 0.15-μ-gate enhancement-mode high-electron mobility transistors utilizing Ir/Ti/Pt/Au gate metallization were fabricated using a new process including a high-temperature gate anneal that is required for Schottky-barrier height enhancement for the Ir-based gate contact. SiNx encapsulation was employed to prevent thermal degradation of device layer during the high-temperature gate anneal. Excellent enhancement-mode operation, with a threshold voltage of 0.1 V and IDSS of 2.1 mA/mm, was realized. Both the annealed and unannealed devices exhibited high gm,max and ID,max 800 mS/mm and 430 mA/mm, respectively. A unity current-gain cutoff frequency fT of 151 GHz and a maximum oscillation frequency fMAX of 172 GHz were achieved. From the dc and RF characteristics, it can be deduced that there was no degradation of the gate contact and the heterostructure due to gate annealing. Furthermore, it was found that the gate diffusion during gate annealing was negligible since no increase in gm,max was observed.

Original languageEnglish
Pages (from-to)873-876
Number of pages4
JournalIEEE Electron Device Letters
Volume27
Issue number11
DOIs
Publication statusPublished - Nov 2006
Externally publishedYes

Fingerprint

Gates (transistor)
High electron mobility transistors
Annealing
Cutoff frequency
Metallizing
Threshold voltage
Encapsulation
Heterojunctions
Pyrolysis
Degradation
Temperature

Keywords

  • Enhancement-mode high-electron mobility transistor (E-HEMT)
  • InP E-HEMT
  • Iridium gate

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

0.15-μm-Gate InAlAs/InGaAs/InP E-HEMTs utilizing Ir/Ti/Pt/Au gate structure. / Kim, Seiyon; Adesida, Ilesanmi.

In: IEEE Electron Device Letters, Vol. 27, No. 11, 11.2006, p. 873-876.

Research output: Contribution to journalArticle

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