1 Bit CMOS current mode digital full adder

Prashob R. Nair, K. K. Ajayan, A. P. James

Research output: Contribution to conferencePaper

Abstract

This paper proposes an improved design of the current mode adder. The circuit operates well at operating voltages of 1.0V. The voltage swing obtained is 0.5V for the SUM node and 0.45V for CARRY node. The performance at frequency of 1 MHz has been studied. Simulations are done on SPICE using BSIM model 3V3.0 for 0.13u real technology. A comparison with respect to the output voltage signal, power and area over the existing design is also made.

Original languageEnglish
Publication statusPublished - Jan 1 2006
EventMIPRO 2006 - 29th International Convention: Microelectronics, Electronics and Electronic Technologies, MEET, Hypermedia and Grid Systems HGS - Opatija, Croatia
Duration: May 22 2006May 26 2006

Other

OtherMIPRO 2006 - 29th International Convention: Microelectronics, Electronics and Electronic Technologies, MEET, Hypermedia and Grid Systems HGS
CountryCroatia
CityOpatija
Period5/22/065/26/06

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Surfaces, Coatings and Films
  • Condensed Matter Physics
  • Atomic and Molecular Physics, and Optics

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    Nair, P. R., Ajayan, K. K., & James, A. P. (2006). 1 Bit CMOS current mode digital full adder. Paper presented at MIPRO 2006 - 29th International Convention: Microelectronics, Electronics and Electronic Technologies, MEET, Hypermedia and Grid Systems HGS, Opatija, Croatia.