Abstract
This paper proposes an improved design of the current mode adder. The circuit operates well at operating voltages of 1.0V. The voltage swing obtained is 0.5V for the SUM node and 0.45V for CARRY node. The performance at frequency of 1 MHz has been studied. Simulations are done on SPICE using BSIM model 3V3.0 for 0.13u real technology. A comparison with respect to the output voltage signal, power and area over the existing design is also made.
| Original language | English |
|---|---|
| Title of host publication | MIPRO 2006 - 29th International Convention Proceedings: Microelectronics, Electronics and Electronic Technologies, MEET, Hypermedia and Grid Systems HGS |
| Publisher | Croatian Society for Information and Communication Technology |
| Volume | 1 |
| Publication status | Published - 2006 |
| Externally published | Yes |
| Event | MIPRO 2006 - 29th International Convention: Microelectronics, Electronics and Electronic Technologies, MEET, Hypermedia and Grid Systems HGS - Opatija, Croatia Duration: May 22 2006 → May 26 2006 |
Other
| Other | MIPRO 2006 - 29th International Convention: Microelectronics, Electronics and Electronic Technologies, MEET, Hypermedia and Grid Systems HGS |
|---|---|
| Country | Croatia |
| City | Opatija |
| Period | 5/22/06 → 5/26/06 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
- Surfaces, Coatings and Films
- Condensed Matter Physics
- Atomic and Molecular Physics, and Optics
Cite this
1 Bit CMOS current mode digital full adder. / Nair, Prashob R.; Ajayan, K. K.; James, A. P.
MIPRO 2006 - 29th International Convention Proceedings: Microelectronics, Electronics and Electronic Technologies, MEET, Hypermedia and Grid Systems HGS. Vol. 1 Croatian Society for Information and Communication Technology, 2006.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - 1 Bit CMOS current mode digital full adder
AU - Nair, Prashob R.
AU - Ajayan, K. K.
AU - James, A. P.
PY - 2006
Y1 - 2006
N2 - This paper proposes an improved design of the current mode adder. The circuit operates well at operating voltages of 1.0V. The voltage swing obtained is 0.5V for the SUM node and 0.45V for CARRY node. The performance at frequency of 1 MHz has been studied. Simulations are done on SPICE using BSIM model 3V3.0 for 0.13u real technology. A comparison with respect to the output voltage signal, power and area over the existing design is also made.
AB - This paper proposes an improved design of the current mode adder. The circuit operates well at operating voltages of 1.0V. The voltage swing obtained is 0.5V for the SUM node and 0.45V for CARRY node. The performance at frequency of 1 MHz has been studied. Simulations are done on SPICE using BSIM model 3V3.0 for 0.13u real technology. A comparison with respect to the output voltage signal, power and area over the existing design is also made.
UR - http://www.scopus.com/inward/record.url?scp=84895868031&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84895868031&partnerID=8YFLogxK
M3 - Conference contribution
VL - 1
BT - MIPRO 2006 - 29th International Convention Proceedings: Microelectronics, Electronics and Electronic Technologies, MEET, Hypermedia and Grid Systems HGS
PB - Croatian Society for Information and Communication Technology
ER -