A 30 Gb/s Integrated Receiver Array for Parallel Optical Interconnects

Nga T. H. Nguyen, Ikechi Augustine Ukaegbu, Hyo-Hoon Park

Research output: Contribution to journalArticle

Abstract

A 30 Gb/s integrated receiver array for parallel optical interconnects with 4 channels have been designed and implemented in a 0.13 µm CMOS technology. To achieve small area and low power consumption while maintaining large bandwidth and high gain, the integrated receiver has been implemented with a regulated cascode (RGC) transimpedance amplifier (TIA), resistive and capacitive degeneration and inductorless limiting amplifier (LA), which employs active feedback and negative capacitance. From the measurement results of the optical module using 850 nm photodiode (PD), the receiver showed a constant single-ended output swing of 320 mV up to 7.5 Gb/s/ch with clear eye diagrams and BER of less than 10-12. With a voltage supply of 1.2 V, a figure of merit (FOM) of 8 mW/Gb/s was obtained with a small chip area per channel of 0.28 mm2/ch.
Original languageEnglish
Pages (from-to)1
Number of pages4
JournalIET Journal of Engineering
Publication statusPublished - Apr 17 2019

Fingerprint Dive into the research topics of 'A 30 Gb/s Integrated Receiver Array for Parallel Optical Interconnects'. Together they form a unique fingerprint.

  • Cite this