A design of HTM spatial pooler for face recognition using memristor-CMOS hybrid circuits

Timur Ibrayev, Alex Pappachen James, Cory Merkel, Dhireesha Kudithipudi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

18 Citations (Scopus)

Abstract

Hierarchical Temporal Memory (HTM) is a machine learning algorithm that is inspired from the working principles of the neocortex, capable of learning, inference, and prediction for bit-encoded inputs. Spatial pooler is an integral part of HTM that is capable of learning and classifying visual data such as objects in images. In this paper, we propose a memristor-CMOS circuit design of spatial pooler and exploit memristors capabilities for emulating the synapses, where the strength of the weights is represented by the state of the memristor. The proposed design is validated on a challenging application of single image per person face recognition problem using AR database resulting in a recognition accuracy of 80%.

Original languageEnglish
Title of host publicationISCAS 2016 - IEEE International Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1254-1257
Number of pages4
Volume2016-July
ISBN (Electronic)9781479953400
DOIs
Publication statusPublished - Jul 29 2016
Event2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016 - Montreal, Canada
Duration: May 22 2016May 25 2016

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2016-July
ISSN (Print)0271-4310

Conference

Conference2016 IEEE International Symposium on Circuits and Systems, ISCAS 2016
CountryCanada
CityMontreal
Period5/22/165/25/16

Keywords

  • feature extraction
  • Hierarchical Temporal Memory
  • machine learning
  • memristor
  • neuromorphic design
  • pattern recognition

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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