A dynamically reconfigurable VLSI processor with hierarchical structure based on a micropacket transfer scheme

Yoshichika Fujioka, Michitaka Kameyama, Martin Lukac

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)

    Abstract

    In this paper we propose improvements to the Micro-packet Transfer scheme in a multi-core device (also called reconfigurable VLSI or Network-on-chip). In particular we propose a new hierarchy based micro-packet control scheme that is especially effective for tasks require large number execution clock steps.

    Original languageEnglish
    Title of host publicationProceedings of the International Conference on Information and Digital Technologies, IDT 2017
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages132-136
    Number of pages5
    ISBN (Electronic)9781509056880
    DOIs
    Publication statusPublished - Sep 1 2017
    Event2017 International Conference on Information and Digital Technologies, IDT 2017 - Zilina, Slovakia
    Duration: Jul 5 2017Jul 7 2017

    Conference

    Conference2017 International Conference on Information and Digital Technologies, IDT 2017
    CountrySlovakia
    CityZilina
    Period7/5/177/7/17

    Fingerprint

    very large scale integration
    central processing units
    Clocks
    clocks
    hierarchies
    chips
    Network-on-chip

    ASJC Scopus subject areas

    • Instrumentation
    • Computer Networks and Communications
    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Safety, Risk, Reliability and Quality

    Cite this

    Fujioka, Y., Kameyama, M., & Lukac, M. (2017). A dynamically reconfigurable VLSI processor with hierarchical structure based on a micropacket transfer scheme. In Proceedings of the International Conference on Information and Digital Technologies, IDT 2017 (pp. 132-136). [8024284] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DT.2017.8024284

    A dynamically reconfigurable VLSI processor with hierarchical structure based on a micropacket transfer scheme. / Fujioka, Yoshichika; Kameyama, Michitaka; Lukac, Martin.

    Proceedings of the International Conference on Information and Digital Technologies, IDT 2017. Institute of Electrical and Electronics Engineers Inc., 2017. p. 132-136 8024284.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Fujioka, Y, Kameyama, M & Lukac, M 2017, A dynamically reconfigurable VLSI processor with hierarchical structure based on a micropacket transfer scheme. in Proceedings of the International Conference on Information and Digital Technologies, IDT 2017., 8024284, Institute of Electrical and Electronics Engineers Inc., pp. 132-136, 2017 International Conference on Information and Digital Technologies, IDT 2017, Zilina, Slovakia, 7/5/17. https://doi.org/10.1109/DT.2017.8024284
    Fujioka Y, Kameyama M, Lukac M. A dynamically reconfigurable VLSI processor with hierarchical structure based on a micropacket transfer scheme. In Proceedings of the International Conference on Information and Digital Technologies, IDT 2017. Institute of Electrical and Electronics Engineers Inc. 2017. p. 132-136. 8024284 https://doi.org/10.1109/DT.2017.8024284
    Fujioka, Yoshichika ; Kameyama, Michitaka ; Lukac, Martin. / A dynamically reconfigurable VLSI processor with hierarchical structure based on a micropacket transfer scheme. Proceedings of the International Conference on Information and Digital Technologies, IDT 2017. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 132-136
    @inproceedings{425b050d1d7445bc858abf3cbec53738,
    title = "A dynamically reconfigurable VLSI processor with hierarchical structure based on a micropacket transfer scheme",
    abstract = "In this paper we propose improvements to the Micro-packet Transfer scheme in a multi-core device (also called reconfigurable VLSI or Network-on-chip). In particular we propose a new hierarchy based micro-packet control scheme that is especially effective for tasks require large number execution clock steps.",
    author = "Yoshichika Fujioka and Michitaka Kameyama and Martin Lukac",
    year = "2017",
    month = "9",
    day = "1",
    doi = "10.1109/DT.2017.8024284",
    language = "English",
    pages = "132--136",
    booktitle = "Proceedings of the International Conference on Information and Digital Technologies, IDT 2017",
    publisher = "Institute of Electrical and Electronics Engineers Inc.",
    address = "United States",

    }

    TY - GEN

    T1 - A dynamically reconfigurable VLSI processor with hierarchical structure based on a micropacket transfer scheme

    AU - Fujioka, Yoshichika

    AU - Kameyama, Michitaka

    AU - Lukac, Martin

    PY - 2017/9/1

    Y1 - 2017/9/1

    N2 - In this paper we propose improvements to the Micro-packet Transfer scheme in a multi-core device (also called reconfigurable VLSI or Network-on-chip). In particular we propose a new hierarchy based micro-packet control scheme that is especially effective for tasks require large number execution clock steps.

    AB - In this paper we propose improvements to the Micro-packet Transfer scheme in a multi-core device (also called reconfigurable VLSI or Network-on-chip). In particular we propose a new hierarchy based micro-packet control scheme that is especially effective for tasks require large number execution clock steps.

    UR - http://www.scopus.com/inward/record.url?scp=85030086035&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=85030086035&partnerID=8YFLogxK

    U2 - 10.1109/DT.2017.8024284

    DO - 10.1109/DT.2017.8024284

    M3 - Conference contribution

    AN - SCOPUS:85030086035

    SP - 132

    EP - 136

    BT - Proceedings of the International Conference on Information and Digital Technologies, IDT 2017

    PB - Institute of Electrical and Electronics Engineers Inc.

    ER -