A dynamically reconfigurable VLSI processor with hierarchical structure based on a micropacket transfer scheme

Yoshichika Fujioka, Michitaka Kameyama, Martin Lukac

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)

    Abstract

    In this paper we propose improvements to the Micro-packet Transfer scheme in a multi-core device (also called reconfigurable VLSI or Network-on-chip). In particular we propose a new hierarchy based micro-packet control scheme that is especially effective for tasks require large number execution clock steps.

    Original languageEnglish
    Title of host publicationProceedings of the International Conference on Information and Digital Technologies, IDT 2017
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Pages132-136
    Number of pages5
    ISBN (Electronic)9781509056880
    DOIs
    Publication statusPublished - Sep 1 2017
    Event2017 International Conference on Information and Digital Technologies, IDT 2017 - Zilina, Slovakia
    Duration: Jul 5 2017Jul 7 2017

    Conference

    Conference2017 International Conference on Information and Digital Technologies, IDT 2017
    CountrySlovakia
    CityZilina
    Period7/5/177/7/17

    ASJC Scopus subject areas

    • Instrumentation
    • Computer Networks and Communications
    • Hardware and Architecture
    • Electrical and Electronic Engineering
    • Safety, Risk, Reliability and Quality

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