Abstract
Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. PR is an important enabler for implementing adaptive systems. However, the design of such systems can be challenging, and this is especially true of the configuration controller. The generally supported methods and IP have low throughput, resulting in long configuration time that precludes PR from systems where this operation needs to be fast. In this paper, we present a high-speed configuration controller that provides several features useful in adaptive systems. The design has been released for use by the wider research community.
| Original language | English |
|---|---|
| Title of host publication | FPT 2012 - 2012 International Conference on Field-Programmable Technology |
| Pages | 61-66 |
| Number of pages | 6 |
| DOIs | |
| Publication status | Published - 2012 |
| Externally published | Yes |
| Event | 2012 International Conference on Field-Programmable Technology, FPT 2012 - Seoul, Korea, Republic of Duration: Dec 10 2012 → Dec 12 2012 |
Conference
| Conference | 2012 International Conference on Field-Programmable Technology, FPT 2012 |
|---|---|
| Country | Korea, Republic of |
| City | Seoul |
| Period | 12/10/12 → 12/12/12 |
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ASJC Scopus subject areas
- Logic
Cite this
A high speed open source controller for FPGA partial reconfiguration. / Vipin, Kizheppatt; Fahmy, Suhaib A.
FPT 2012 - 2012 International Conference on Field-Programmable Technology. 2012. p. 61-66 6412113.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - A high speed open source controller for FPGA partial reconfiguration
AU - Vipin, Kizheppatt
AU - Fahmy, Suhaib A.
PY - 2012
Y1 - 2012
N2 - Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. PR is an important enabler for implementing adaptive systems. However, the design of such systems can be challenging, and this is especially true of the configuration controller. The generally supported methods and IP have low throughput, resulting in long configuration time that precludes PR from systems where this operation needs to be fast. In this paper, we present a high-speed configuration controller that provides several features useful in adaptive systems. The design has been released for use by the wider research community.
AB - Partial Reconfiguration (PR) is an advanced technique, which improves the flexibility of FPGAs by allowing portions of a design to be reconfigured at runtime by overwriting parts of the configuration memory. PR is an important enabler for implementing adaptive systems. However, the design of such systems can be challenging, and this is especially true of the configuration controller. The generally supported methods and IP have low throughput, resulting in long configuration time that precludes PR from systems where this operation needs to be fast. In this paper, we present a high-speed configuration controller that provides several features useful in adaptive systems. The design has been released for use by the wider research community.
UR - http://www.scopus.com/inward/record.url?scp=84874038230&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84874038230&partnerID=8YFLogxK
U2 - 10.1109/FPT.2012.6412113
DO - 10.1109/FPT.2012.6412113
M3 - Conference contribution
SN - 9781467328449
SP - 61
EP - 66
BT - FPT 2012 - 2012 International Conference on Field-Programmable Technology
ER -