AnalogHTM: Memristive Spatial Pooler Learning with Backpropagation

Olga Krestinskaya, Alex Pappachen James

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Spatial pooler is responsible for feature extraction in Hierarchical Temporal Memory (HTM). In this paper, we present analog backpropagation learning circuits integrated to the memristive circuit design of spatial pooler. Using 0.18μm CMOS technology and TiOx memristor models, the maximum on-chip area and power consumption of the proposed design are 8335.074μm2 and 51.55mW, respectively. The system is tested for a face recognition problem AR face database achieving a recognition accuracy of 90%.

Original languageEnglish
Title of host publicationProceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages262-266
Number of pages5
ISBN (Electronic)9781538678848
DOIs
Publication statusPublished - Mar 1 2019
Event1st IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019 - Hsinchu, Taiwan
Duration: Mar 18 2019Mar 20 2019

Publication series

NameProceedings 2019 IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019

Conference

Conference1st IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2019
CountryTaiwan
CityHsinchu
Period3/18/193/20/19

Keywords

  • backpropagation
  • HTM
  • learning
  • memristor
  • Spatial Pooler

ASJC Scopus subject areas

  • Artificial Intelligence
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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