Analysis of faults in reversible computing

Martin Lukac, Michitaka Kameyama, Marek Perkowski, Pawel Kerntopf, Claudio Moraga

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper we describe faults that can occur in reversible circuits. In particular, we focus on comparison of faults that can appear in classical circuits with faults that can occur in quantum technology. The analysis is generalized from the point of view of technologies such as information reversible and energy reversible. We show that contrary to classical non-reversible transistor based circuits, it is necessary to specify what type of reversible circuit we are describing. Moreover the level of faults and their analysis must be revised to precisely capture the effects and properties of quantum gates and quantum circuits. By not doing so the available testing approaches adapted from classical circuits could not be able to properly developed to relevant faults. In addition, if the classical faults are directly applied without revision and modifications, the presented testing procedure would be testing for such faults that cannot physically occur in the given implementation of reversible circuits.

Original languageEnglish
Title of host publicationProceedings of The International Symposium on Multiple-Valued Logic
PublisherIEEE Computer Society
Pages115-120
Number of pages6
ISBN (Print)9781479935345
DOIs
Publication statusPublished - 2014
Externally publishedYes
Event44th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2014 - Bremen, Germany
Duration: May 19 2014May 21 2014

Other

Other44th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2014
CountryGermany
CityBremen
Period5/19/145/21/14

Fingerprint

Fault
Networks (circuits)
Computing
Testing
Quantum Circuits
Transistors
Necessary
Energy

Keywords

  • Quantum Faults
  • Quantum Implementation
  • Reversible Faults
  • Reversible Logic

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

Cite this

Lukac, M., Kameyama, M., Perkowski, M., Kerntopf, P., & Moraga, C. (2014). Analysis of faults in reversible computing. In Proceedings of The International Symposium on Multiple-Valued Logic (pp. 115-120). [6845006] IEEE Computer Society. https://doi.org/10.1109/ISMVL.2014.28

Analysis of faults in reversible computing. / Lukac, Martin; Kameyama, Michitaka; Perkowski, Marek; Kerntopf, Pawel; Moraga, Claudio.

Proceedings of The International Symposium on Multiple-Valued Logic. IEEE Computer Society, 2014. p. 115-120 6845006.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lukac, M, Kameyama, M, Perkowski, M, Kerntopf, P & Moraga, C 2014, Analysis of faults in reversible computing. in Proceedings of The International Symposium on Multiple-Valued Logic., 6845006, IEEE Computer Society, pp. 115-120, 44th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2014, Bremen, Germany, 5/19/14. https://doi.org/10.1109/ISMVL.2014.28
Lukac M, Kameyama M, Perkowski M, Kerntopf P, Moraga C. Analysis of faults in reversible computing. In Proceedings of The International Symposium on Multiple-Valued Logic. IEEE Computer Society. 2014. p. 115-120. 6845006 https://doi.org/10.1109/ISMVL.2014.28
Lukac, Martin ; Kameyama, Michitaka ; Perkowski, Marek ; Kerntopf, Pawel ; Moraga, Claudio. / Analysis of faults in reversible computing. Proceedings of The International Symposium on Multiple-Valued Logic. IEEE Computer Society, 2014. pp. 115-120
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