Automated partitioning for partial reconfiguration design of adaptive systems

Kizheppatt Vipin, Suhaib A. Fahmy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Citations (Scopus)

Abstract

Adaptive systems have the ability to respond to environmental conditions by modifying their processing at runtime. This can be implemented by using partial reconfiguration (PR) on FPGAs. However, designing such systems requires specialist architecture knowledge and an understanding of the mechanics of reconfiguration, as the design process is completely manual. One design choice that must be made, which impacts system efficiency significantly, is how to group reconfigurable modules and assign them to reconfigurable regions on the FPGA. In this paper, we present an approach, based on graph clustering, that finds a partitioning that minimises reconfiguration time, given an application description and target FPGA. The resulting allocation respects all the constraints set by the official tool flow while raising the level of design abstraction, allowing non-expert designers to leverage this capability of FPGAs.

Original languageEnglish
Title of host publicationProceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013
PublisherIEEE Computer Society
Pages172-181
Number of pages10
DOIs
Publication statusPublished - 2013
Externally publishedYes
Event2013 IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013 - Boston, MA, United States
Duration: May 20 2013May 24 2013

Conference

Conference2013 IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013
CountryUnited States
CityBoston, MA
Period5/20/135/24/13

Fingerprint

Adaptive systems
Adaptive Systems
Reconfiguration
Field Programmable Gate Array
Field programmable gate arrays (FPGA)
Partitioning
Partial
Graph Clustering
Leverage
Design Process
Mechanics
Assign
Minimise
Module
Target
Design
Processing

Keywords

  • design automation
  • Field programmable gate arrays
  • partial reconfiguration

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Software
  • Theoretical Computer Science

Cite this

Vipin, K., & Fahmy, S. A. (2013). Automated partitioning for partial reconfiguration design of adaptive systems. In Proceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013 (pp. 172-181). [6650884] IEEE Computer Society. https://doi.org/10.1109/IPDPSW.2013.119

Automated partitioning for partial reconfiguration design of adaptive systems. / Vipin, Kizheppatt; Fahmy, Suhaib A.

Proceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013. IEEE Computer Society, 2013. p. 172-181 6650884.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Vipin, K & Fahmy, SA 2013, Automated partitioning for partial reconfiguration design of adaptive systems. in Proceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013., 6650884, IEEE Computer Society, pp. 172-181, 2013 IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013, Boston, MA, United States, 5/20/13. https://doi.org/10.1109/IPDPSW.2013.119
Vipin K, Fahmy SA. Automated partitioning for partial reconfiguration design of adaptive systems. In Proceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013. IEEE Computer Society. 2013. p. 172-181. 6650884 https://doi.org/10.1109/IPDPSW.2013.119
Vipin, Kizheppatt ; Fahmy, Suhaib A. / Automated partitioning for partial reconfiguration design of adaptive systems. Proceedings - IEEE 27th International Parallel and Distributed Processing Symposium Workshops and PhD Forum, IPDPSW 2013. IEEE Computer Society, 2013. pp. 172-181
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