CMOS-Memristive Analog Multiplier Design

Ileskhan Kalysh, Olga Krestinskaya, Alex James Pappachen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The implementation of analog multiplication process in analog domain is a challenging task, which involves complex circuits with large on-chip area and high power consumption to achieve highly linear multiplication performance. Therefore, such multipliers cannot be used for large scale problems. This paper addresses these issues and proposes four quadrant analog CMOS-memristive analog multiplier design aiming to reduce on-chip area and power consumption of the circuit. The multiplier is designed using TSMC 180 nm CMOS technology and simulated in SPICE. The proposed multiplier allows to reduce on-chip area and power consumption by 25% and 5%, respectively.

Original languageEnglish
Title of host publicationProceedings of the 2nd International Conference on Computing and Network Communications, CoCoNet 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1-5
Number of pages5
ISBN (Electronic)9781538659281
DOIs
Publication statusPublished - Sep 28 2018
Event2nd International Conference on Computing and Network Communications, CoCoNet 2018 - Astana, Kazakhstan
Duration: Aug 15 2018Aug 17 2018

Conference

Conference2nd International Conference on Computing and Network Communications, CoCoNet 2018
CountryKazakhstan
CityAstana
Period8/15/188/17/18

Fingerprint

Electric power utilization
Networks (circuits)
SPICE

Keywords

  • Analog multiplier
  • CMOS
  • Memristor

ASJC Scopus subject areas

  • Computer Networks and Communications
  • Computer Science Applications
  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Kalysh, I., Krestinskaya, O., & James Pappachen, A. (2018). CMOS-Memristive Analog Multiplier Design. In Proceedings of the 2nd International Conference on Computing and Network Communications, CoCoNet 2018 (pp. 1-5). [8476883] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CoCoNet.2018.8476883

CMOS-Memristive Analog Multiplier Design. / Kalysh, Ileskhan; Krestinskaya, Olga; James Pappachen, Alex.

Proceedings of the 2nd International Conference on Computing and Network Communications, CoCoNet 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 1-5 8476883.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kalysh, I, Krestinskaya, O & James Pappachen, A 2018, CMOS-Memristive Analog Multiplier Design. in Proceedings of the 2nd International Conference on Computing and Network Communications, CoCoNet 2018., 8476883, Institute of Electrical and Electronics Engineers Inc., pp. 1-5, 2nd International Conference on Computing and Network Communications, CoCoNet 2018, Astana, Kazakhstan, 8/15/18. https://doi.org/10.1109/CoCoNet.2018.8476883
Kalysh I, Krestinskaya O, James Pappachen A. CMOS-Memristive Analog Multiplier Design. In Proceedings of the 2nd International Conference on Computing and Network Communications, CoCoNet 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 1-5. 8476883 https://doi.org/10.1109/CoCoNet.2018.8476883
Kalysh, Ileskhan ; Krestinskaya, Olga ; James Pappachen, Alex. / CMOS-Memristive Analog Multiplier Design. Proceedings of the 2nd International Conference on Computing and Network Communications, CoCoNet 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 1-5
@inproceedings{72fcf22da37742ce8290859744868bc1,
title = "CMOS-Memristive Analog Multiplier Design",
abstract = "The implementation of analog multiplication process in analog domain is a challenging task, which involves complex circuits with large on-chip area and high power consumption to achieve highly linear multiplication performance. Therefore, such multipliers cannot be used for large scale problems. This paper addresses these issues and proposes four quadrant analog CMOS-memristive analog multiplier design aiming to reduce on-chip area and power consumption of the circuit. The multiplier is designed using TSMC 180 nm CMOS technology and simulated in SPICE. The proposed multiplier allows to reduce on-chip area and power consumption by 25{\%} and 5{\%}, respectively.",
keywords = "Analog multiplier, CMOS, Memristor",
author = "Ileskhan Kalysh and Olga Krestinskaya and {James Pappachen}, Alex",
year = "2018",
month = "9",
day = "28",
doi = "10.1109/CoCoNet.2018.8476883",
language = "English",
pages = "1--5",
booktitle = "Proceedings of the 2nd International Conference on Computing and Network Communications, CoCoNet 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
address = "United States",

}

TY - GEN

T1 - CMOS-Memristive Analog Multiplier Design

AU - Kalysh, Ileskhan

AU - Krestinskaya, Olga

AU - James Pappachen, Alex

PY - 2018/9/28

Y1 - 2018/9/28

N2 - The implementation of analog multiplication process in analog domain is a challenging task, which involves complex circuits with large on-chip area and high power consumption to achieve highly linear multiplication performance. Therefore, such multipliers cannot be used for large scale problems. This paper addresses these issues and proposes four quadrant analog CMOS-memristive analog multiplier design aiming to reduce on-chip area and power consumption of the circuit. The multiplier is designed using TSMC 180 nm CMOS technology and simulated in SPICE. The proposed multiplier allows to reduce on-chip area and power consumption by 25% and 5%, respectively.

AB - The implementation of analog multiplication process in analog domain is a challenging task, which involves complex circuits with large on-chip area and high power consumption to achieve highly linear multiplication performance. Therefore, such multipliers cannot be used for large scale problems. This paper addresses these issues and proposes four quadrant analog CMOS-memristive analog multiplier design aiming to reduce on-chip area and power consumption of the circuit. The multiplier is designed using TSMC 180 nm CMOS technology and simulated in SPICE. The proposed multiplier allows to reduce on-chip area and power consumption by 25% and 5%, respectively.

KW - Analog multiplier

KW - CMOS

KW - Memristor

UR - http://www.scopus.com/inward/record.url?scp=85055982575&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85055982575&partnerID=8YFLogxK

U2 - 10.1109/CoCoNet.2018.8476883

DO - 10.1109/CoCoNet.2018.8476883

M3 - Conference contribution

SP - 1

EP - 5

BT - Proceedings of the 2nd International Conference on Computing and Network Communications, CoCoNet 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -