Constrained minimization of switched capacitor converter equivalent resistance by adjusting transistor sizes and duty cycles

Yerzhan Mustafa, Han Yin, Yan Lu, Alex Ruderman

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

This paper presents a novel optimization technique for Switched Capacitor Converters (SCCs). The optimization focuses on minimizing the SCC equivalent resistance by adjusting MOSFET widths and switching duty cycles. The optimized SCC parameters are obtained from numerical optimization with constant total transistor width and switching period constraints. The transistor carrier mobilities and gate-to-source voltages are accounted during the optimization. A Fibonacci SCC with two flying capacitors is used as an example and is simulated in a 65 ​nm low-power process. By comparing SCC parameters before and after the optimization, we obtain certain performance improvements. Particularly, at a switching frequency of 10MHz and 50Ω load, the optimized design shows improvement in average and minimum output voltage parameters by 2.5% and 4.1%, respectively, which are caused by 20.6% reduction of the equivalent resistance. The output voltage ripple is also decreased by 22.4%. By sweeping the duty cycle and transistor widths in simulation, the optimized parameters show nearly the best performance.

Original languageEnglish
Article number105061
JournalMicroelectronics Journal
Volume112
DOIs
Publication statusPublished - Jun 2021

Keywords

  • Constrained optimization
  • Equivalent resistance
  • Switched Capacitor Converter (SCC)
  • VLSI

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

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