Design of Analog-type High-speed SerDes Using Digital Components for Optical Chip-to-chip Link

Jamshid Sangirov, Nga T. H. Nguyen, Trong-Hieu Ngo, Ikechi Augustine Ukaegbu, Tae-Woo Lee, Mu-Hee Cho, Hyo-Hoon Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

An analog-type high-speed serializer/deserializer (SerDes) has been designed for optical links especially between CPU and memory. The circuit uses a system clock and its phases to multiplex data to the serial link which avoids the need for a PLL-based high frequency clock generation used in serializing parallel data as in conventional SerDes design. The multiplexed link combined with the de-serializing clock is used as a reference signal for de-serialization. The SerDes is being designed in a 0.13 μm Si-CMOS technology. The fabricated serializer has a core chip size of 360 x750 μm2. Power dissipation for the SerDes is 71.4 mW operating up to 6.5 Gbps.
Original languageEnglish
Title of host publicationOptoelectronic Interconnects and Component Integration IX, 7607, SPIE Photonics West
PublisherSPIE
Pages1B1 - B9
Number of pages9
Publication statusPublished - Feb 24 2010

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