DyRACT: A partial reconfiguration enabled accelerator and test platform

Kizheppatt Vipin, Suhaib A. Fahmy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

20 Citations (Scopus)

Abstract

Integrating FPGAs with a general purpose computer remains difficult, but recent efforts have resulted in open frameworks that offer a software API and hardware interface to allow easier integration. However, such systems only support static FPGA designs. With the addition of partial reconfiguration (PR) support, such frameworks can enable more effective use of FPGAs. Now, designers can incorporate hardware accelerators within their software applications, and these can be loaded dynamically as required. We present a PR-enabled FPGA platform that allows user modules to be loaded onto the FPGA, inputs to be applied, results obtained, and functions to be swapped at runtime. The interface and PR management logic are part of the static region, while multiple accelerators can be loaded using high level functions provided by the API. Reconfiguration and data transfer are both managed over the PCIe interface from the host PC, with communication throughput of more than 1.5 GB/s (75% of peak PCIe bandwidth) and reconfiguration of a large accelerator in 20 ms.

Original languageEnglish
Title of host publicationConference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9783000446450
DOIs
Publication statusPublished - Oct 16 2014
Externally publishedYes
Event24th International Conference on Field Programmable Logic and Applications, FPL 2014 - Munich, Germany
Duration: Sep 1 2014Sep 5 2014

Conference

Conference24th International Conference on Field Programmable Logic and Applications, FPL 2014
CountryGermany
CityMunich
Period9/1/149/5/14

Fingerprint

Particle accelerators
Field programmable gate arrays (FPGA)
Application programming interfaces (API)
Computer hardware
General purpose computers
Data transfer
Application programs
Interfaces (computer)
Throughput
Bandwidth
Communication

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture

Cite this

Vipin, K., & Fahmy, S. A. (2014). DyRACT: A partial reconfiguration enabled accelerator and test platform. In Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014 [6927507] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/FPL.2014.6927507

DyRACT : A partial reconfiguration enabled accelerator and test platform. / Vipin, Kizheppatt; Fahmy, Suhaib A.

Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6927507.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Vipin, K & Fahmy, SA 2014, DyRACT: A partial reconfiguration enabled accelerator and test platform. in Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014., 6927507, Institute of Electrical and Electronics Engineers Inc., 24th International Conference on Field Programmable Logic and Applications, FPL 2014, Munich, Germany, 9/1/14. https://doi.org/10.1109/FPL.2014.6927507
Vipin K, Fahmy SA. DyRACT: A partial reconfiguration enabled accelerator and test platform. In Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6927507 https://doi.org/10.1109/FPL.2014.6927507
Vipin, Kizheppatt ; Fahmy, Suhaib A. / DyRACT : A partial reconfiguration enabled accelerator and test platform. Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 2014.
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