Abstract
Integrating FPGAs with a general purpose computer remains difficult, but recent efforts have resulted in open frameworks that offer a software API and hardware interface to allow easier integration. However, such systems only support static FPGA designs. With the addition of partial reconfiguration (PR) support, such frameworks can enable more effective use of FPGAs. Now, designers can incorporate hardware accelerators within their software applications, and these can be loaded dynamically as required. We present a PR-enabled FPGA platform that allows user modules to be loaded onto the FPGA, inputs to be applied, results obtained, and functions to be swapped at runtime. The interface and PR management logic are part of the static region, while multiple accelerators can be loaded using high level functions provided by the API. Reconfiguration and data transfer are both managed over the PCIe interface from the host PC, with communication throughput of more than 1.5 GB/s (75% of peak PCIe bandwidth) and reconfiguration of a large accelerator in 20 ms.
| Original language | English |
|---|---|
| Title of host publication | Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Electronic) | 9783000446450 |
| DOIs | |
| Publication status | Published - Oct 16 2014 |
| Externally published | Yes |
| Event | 24th International Conference on Field Programmable Logic and Applications, FPL 2014 - Munich, Germany Duration: Sep 1 2014 → Sep 5 2014 |
Conference
| Conference | 24th International Conference on Field Programmable Logic and Applications, FPL 2014 |
|---|---|
| Country | Germany |
| City | Munich |
| Period | 9/1/14 → 9/5/14 |
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ASJC Scopus subject areas
- Computer Science Applications
- Hardware and Architecture
Cite this
DyRACT : A partial reconfiguration enabled accelerator and test platform. / Vipin, Kizheppatt; Fahmy, Suhaib A.
Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6927507.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - DyRACT
T2 - A partial reconfiguration enabled accelerator and test platform
AU - Vipin, Kizheppatt
AU - Fahmy, Suhaib A.
PY - 2014/10/16
Y1 - 2014/10/16
N2 - Integrating FPGAs with a general purpose computer remains difficult, but recent efforts have resulted in open frameworks that offer a software API and hardware interface to allow easier integration. However, such systems only support static FPGA designs. With the addition of partial reconfiguration (PR) support, such frameworks can enable more effective use of FPGAs. Now, designers can incorporate hardware accelerators within their software applications, and these can be loaded dynamically as required. We present a PR-enabled FPGA platform that allows user modules to be loaded onto the FPGA, inputs to be applied, results obtained, and functions to be swapped at runtime. The interface and PR management logic are part of the static region, while multiple accelerators can be loaded using high level functions provided by the API. Reconfiguration and data transfer are both managed over the PCIe interface from the host PC, with communication throughput of more than 1.5 GB/s (75% of peak PCIe bandwidth) and reconfiguration of a large accelerator in 20 ms.
AB - Integrating FPGAs with a general purpose computer remains difficult, but recent efforts have resulted in open frameworks that offer a software API and hardware interface to allow easier integration. However, such systems only support static FPGA designs. With the addition of partial reconfiguration (PR) support, such frameworks can enable more effective use of FPGAs. Now, designers can incorporate hardware accelerators within their software applications, and these can be loaded dynamically as required. We present a PR-enabled FPGA platform that allows user modules to be loaded onto the FPGA, inputs to be applied, results obtained, and functions to be swapped at runtime. The interface and PR management logic are part of the static region, while multiple accelerators can be loaded using high level functions provided by the API. Reconfiguration and data transfer are both managed over the PCIe interface from the host PC, with communication throughput of more than 1.5 GB/s (75% of peak PCIe bandwidth) and reconfiguration of a large accelerator in 20 ms.
UR - http://www.scopus.com/inward/record.url?scp=84911092090&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84911092090&partnerID=8YFLogxK
U2 - 10.1109/FPL.2014.6927507
DO - 10.1109/FPL.2014.6927507
M3 - Conference contribution
AN - SCOPUS:84911092090
BT - Conference Digest - 24th International Conference on Field Programmable Logic and Applications, FPL 2014
PB - Institute of Electrical and Electronics Engineers Inc.
ER -