Abstract
Purpose: The purpose of this paper is to present a new approach to edge detection using semiconductor flash memory networks having scalable and parallel hardware architecture. Design/methodology/approach: A flash cell can store multiple states by controlling its voltage threshold. The equivalent resistance of the operation states controlled by threshold voltage of flash cell gives out different combinations of logic 0 and 1 states. The paper explores this basic feature of flash memory in designing a resistance change memory network for implementing novel edge detector hardware. This approach of detecting the edges is inspired from the spatial change detection ability of the human visual system. Findings: The proposed approach consumes less number of electronic components for its implementation, and outperforms the conventional approaches of edge detection with respect to the processing speed, scalability and ease of design. It is also demonstrated to provide edges invariant to changes in the direction of the spatial change in the images. Research limitations/implications: This research brings about a new direction in the development of edge detection, in terms of developing high-speed parallel processing edge detection and imaging circuits. Practical implications: The proposed approach reduces the implementation complexity by removing the need to have convolution operations for spatial edge filtering. Originality/value: This paper presents one of the first edge detection approaches that is purely a hardware oriented design, uses resistance of flash memory to form edge detector cells, and one that does not use computational operations such as additions or multiplications for its implementation.
| Original language | English |
|---|---|
| Pages (from-to) | 79-94 |
| Number of pages | 16 |
| Journal | International Journal of Intelligent Computing and Cybernetics |
| Volume | 7 |
| Issue number | 1 |
| DOIs | |
| Publication status | Published - 2014 |
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Keywords
- Cognitive systems
- Evolvable hardware
- Image processing
ASJC Scopus subject areas
- Computer Science(all)
Cite this
Edge detection using resistive threshold logic networks with CMOS flash memories. / James, Alex Pappachen; Pachentavida, Anusha; Sugathan, Sherin.
In: International Journal of Intelligent Computing and Cybernetics, Vol. 7, No. 1, 2014, p. 79-94.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Edge detection using resistive threshold logic networks with CMOS flash memories
AU - James, Alex Pappachen
AU - Pachentavida, Anusha
AU - Sugathan, Sherin
PY - 2014
Y1 - 2014
N2 - Purpose: The purpose of this paper is to present a new approach to edge detection using semiconductor flash memory networks having scalable and parallel hardware architecture. Design/methodology/approach: A flash cell can store multiple states by controlling its voltage threshold. The equivalent resistance of the operation states controlled by threshold voltage of flash cell gives out different combinations of logic 0 and 1 states. The paper explores this basic feature of flash memory in designing a resistance change memory network for implementing novel edge detector hardware. This approach of detecting the edges is inspired from the spatial change detection ability of the human visual system. Findings: The proposed approach consumes less number of electronic components for its implementation, and outperforms the conventional approaches of edge detection with respect to the processing speed, scalability and ease of design. It is also demonstrated to provide edges invariant to changes in the direction of the spatial change in the images. Research limitations/implications: This research brings about a new direction in the development of edge detection, in terms of developing high-speed parallel processing edge detection and imaging circuits. Practical implications: The proposed approach reduces the implementation complexity by removing the need to have convolution operations for spatial edge filtering. Originality/value: This paper presents one of the first edge detection approaches that is purely a hardware oriented design, uses resistance of flash memory to form edge detector cells, and one that does not use computational operations such as additions or multiplications for its implementation.
AB - Purpose: The purpose of this paper is to present a new approach to edge detection using semiconductor flash memory networks having scalable and parallel hardware architecture. Design/methodology/approach: A flash cell can store multiple states by controlling its voltage threshold. The equivalent resistance of the operation states controlled by threshold voltage of flash cell gives out different combinations of logic 0 and 1 states. The paper explores this basic feature of flash memory in designing a resistance change memory network for implementing novel edge detector hardware. This approach of detecting the edges is inspired from the spatial change detection ability of the human visual system. Findings: The proposed approach consumes less number of electronic components for its implementation, and outperforms the conventional approaches of edge detection with respect to the processing speed, scalability and ease of design. It is also demonstrated to provide edges invariant to changes in the direction of the spatial change in the images. Research limitations/implications: This research brings about a new direction in the development of edge detection, in terms of developing high-speed parallel processing edge detection and imaging circuits. Practical implications: The proposed approach reduces the implementation complexity by removing the need to have convolution operations for spatial edge filtering. Originality/value: This paper presents one of the first edge detection approaches that is purely a hardware oriented design, uses resistance of flash memory to form edge detector cells, and one that does not use computational operations such as additions or multiplications for its implementation.
KW - Cognitive systems
KW - Evolvable hardware
KW - Image processing
UR - http://www.scopus.com/inward/record.url?scp=84898935614&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84898935614&partnerID=8YFLogxK
U2 - 10.1108/IJICC-06-2013-0032
DO - 10.1108/IJICC-06-2013-0032
M3 - Article
VL - 7
SP - 79
EP - 94
JO - International Journal of Intelligent Computing and Cybernetics
JF - International Journal of Intelligent Computing and Cybernetics
SN - 1756-378X
IS - 1
ER -