Deflection-routed FPGA overlay NoCs such as Hoplite suffer from high worst-case routing latencies due to the penalty of deflections at large system sizes. Segmentation of communication channels in such NoCs can (1) reduce worst-case packet routing latencies for FPGA traffic, (2) enable efficient composition of multi-application NoC workloads, and (3) ease the burden of supporting Partial Reconfiguration (PR) for FPGAs. We use segmentation of the NoC links by inserting isolation multiplexers along NoC links to split traffic into different regions. This segmentation reduces routing latencies by localizing the deflected packets to stay within the segmented region. This can be done either statically using configuration bits that can be changed per application phase ≈1000s of cycles or completely dynamically on a per-cycle basis based on packet addresses. For the Xilinx VC709 FPGA board, we build an 8×8 deflection-routed NoC, with 4×4 statically fracturable regions having 256b-wide links with 6% extra LUT resources and no extra pipelining cost to support fracturing while running at >200 MHz. We comprehensively outperform the CONNECT Torus NoC by 2-3× across various traffic patterns while using 4-7× less FPGA resources. When considering real-world traffic extracted from Sniper simulations of multi-processor PARSEC benchmarks, we observe up to 2.7× improvement in throughput for 8×8 NoC with static segmentation. With fully dynamic segmentation applied to large 30×7 NoC with 300b links, hosting a 1,680-core parallel processor, segmenting the NoC into six 5×7 segments uses an additional 1% of device LUTs but improves throughput by as much as 2.5× for LOCAL traffic.