Enhancement-mode InAlAs/InGaAs/InP HEMTs with Ir-based gate metallization

S. Kim, I. Adesida, H. Hwang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The reliability of high electron mobility transistors (HEMTs) significantly depends on the stability of the gate Schottky contact to the semiconductor. Gate sinking during the fabrication and device operation alters transconductance, gate capacitance, and threshold voltage, which are crucial device parameters for modeling HEMT devices and designing circuits. In particular for enhancement-mode InAlAs/InGaAs/InP HEMTs (eHEMTs) where thermally-treated Pt is utilized as the gate metallization, thermal stability has always constituted a problem due to the diffusion of Pt. Although aspects of this diffusion are utilized to enhance e-mode behavior, no quantitative measurements have been conducted to estimate the diffusion depth of Pt in InAlAs. Further, it would be preferable to develop a metallization scheme where the Schottky contact barrier height is similar to that of Pt but with a much lower diffusivity. To this end, we have developed a gate metal structure based on Ir for InAlAs/InGaAs/InP HEMTs and investigated its thermal stability in comparison to the conventional Pt-based contact. A 0.15 μm-gatelength eHEMT utilizing Ir/Ti/Pt/Au gate was fabricated to demonstrate the potential of Ir-based gate technology. In the first experiments, we conducted C-V measurements on 20 μm-gate In 0.52Al 0.48As/In 0.53Ga 0.47As/InP HEMTs (FATFETs) to investigate gate metal diffusion induced by thermal treatments. FATFETs with Ir/Ti/Pt/Au and Pt/Ti/Pt/Au gates were treated in a N 2-purged furnace at 250°C for periods up to 18 min. Gate capacitances were measured with an Agilent 4182 C-V meter at 1 MHz at room temperature. Cross sectional transmission electron microscopy (TEM) was utilized to directly observe the diffusion depths and compared with those extracted from C-V measurements. Secondly, 0.15 μm-gatelength InAlAs/InGaAs/InP eHEMTs were fabricated on a specially designed heterostructure. Hall measurements on the materials showed a sheet density of 1.2×10 12 cm -2 and a mobility of 7640 cm 2/V.s. The device fabrication consisted of a mesa isolation step, T-gate formation by electron beam lithography and lift-off, gate recessing, and Ir/Ti/Pt/Au gate metal stack deposition. Then gate metal structure was covered by SiN x cap layer and annealed in N 2-purged furnace at 525°C for l min to enhance the Schottky barrier height for enhancement-mode operation. Finally, alloyed AuGe/Ni/Au ohmic contact was formed and Ti/Pt/Au overlay metal structure was deposited. DC and RF characteristics were measured with HP 4142B semiconductor parameter analyzer and HP 8510C network analyzer, respectively. Figure 1 shows the C-V measurement results for FATFETs with Ir/Ti/Pt/Au gate and Pt/Ti/Pt/Au gate metallizations. The increase in the maximum gate capacitance of the Pt-contacted devices indicates that the thickness of InAlAs Schottky contact layer decreased as a result of gate metal diffusion. No noticeable change in the maximum capacitance is observed for Ir-contact devices. The shift of C-V curves, which is related to the increase of threshold voltage, is attributed to the enhancement of Schottky barrier height and gate metal diffusion. Since the change of capacitance of Ir-based contact is smaller than that of Pt-based contact, we can deduce that the Ir-based gate contact has superior thermal stability with less metal diffusion. The diffusion depths were extracted by fitting C-V curves to simulation results. The diffusion depth of Ir/Ti/Pt/Au is negligibly small while that of Pt/Ti/Pt/Au contact increases as annealing time increases. The diffusion depth of Pt after 18 min annealing was estimated to be ∼7 nm; this was verified with cross sectional transmission electron microscopy as shown in Figure 2. The diffusion depth for Ir was estimated to be below 1 nm. Figure 3 shows the DC characteristics of a 0.15 μm Ir/Ti/Pt/Au gate eHEMT with and without gate annealing. Enhancement mode operation with a threshold voltage of 0.1 V was realized for the gate-annealed device. Since both the annealed and unannealed devices exhibited high g m and drain current of 800 mS/mm and 420 mS/mm, respectively, it can be deduced that there was no degradation of the gate contact and heterostructures during the gate annealing. Furthermore, it is clear that the gate diffusion during gate annealing is very small since no increase of maximum transconductance is observed. The RF performances of the eHEMT as shown in Figure 4 were an f t and an f max of 155 GHz and 172 GHz, respectively. Details of the device fabrication and complete characterization will be presented at the conference. The Ir-based metallization is also useful for depletion-mode devices.

Original languageEnglish
Title of host publication63rd Device Research Conference Digest, DRC'05
Pages259-260
Number of pages2
DOIs
Publication statusPublished - Dec 1 2005
Event63rd Device Research Conference, DRC'05 - Santa Clara, CA, United States
Duration: Jun 20 2005Jun 22 2005

Publication series

NameDevice Research Conference - Conference Digest, DRC
Volume2005
ISSN (Print)1548-3770

Other

Other63rd Device Research Conference, DRC'05
CountryUnited States
CitySanta Clara, CA
Period6/20/056/22/05

ASJC Scopus subject areas

  • Engineering(all)

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