Abstract
Hierarchical temporal memory (HTM) is a neuromorphic algorithm that emulates sparsity, hierarchy and modularity resembling the working principles of neocortex. Feature encoding is an important step to create sparse binary patterns. This sparsity is introduced by the binary weights and random weight assignment in the initialization stage of the HTM. We propose the alternative deterministic method for the HTM initialization stage, which connects the HTM weights to the input data and preserves natural sparsity of the input information. Further, we introduce the hardware implementation of the deterministic approach and compare it to the traditional HTM and existing hardware implementation. We test the proposed approach on the face recognition problem and show that it outperforms the conventional HTM approach.
| Original language | English |
|---|---|
| Pages (from-to) | 1-9 |
| Number of pages | 9 |
| Journal | Analog Integrated Circuits and Signal Processing |
| DOIs | |
| Publication status | Accepted/In press - Mar 15 2018 |
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Keywords
- Analog circuits
- Hierarchical temporal memory
- Memristors
- Rule based approach
- Spatial Pooler
ASJC Scopus subject areas
- Signal Processing
- Hardware and Architecture
- Surfaces, Coatings and Films
Cite this
Feature extraction without learning in an analog spatial pooler memristive-CMOS circuit design of hierarchical temporal memory. / Krestinskaya, Olga; James, Alex Pappachen.
In: Analog Integrated Circuits and Signal Processing, 15.03.2018, p. 1-9.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Feature extraction without learning in an analog spatial pooler memristive-CMOS circuit design of hierarchical temporal memory
AU - Krestinskaya, Olga
AU - James, Alex Pappachen
PY - 2018/3/15
Y1 - 2018/3/15
N2 - Hierarchical temporal memory (HTM) is a neuromorphic algorithm that emulates sparsity, hierarchy and modularity resembling the working principles of neocortex. Feature encoding is an important step to create sparse binary patterns. This sparsity is introduced by the binary weights and random weight assignment in the initialization stage of the HTM. We propose the alternative deterministic method for the HTM initialization stage, which connects the HTM weights to the input data and preserves natural sparsity of the input information. Further, we introduce the hardware implementation of the deterministic approach and compare it to the traditional HTM and existing hardware implementation. We test the proposed approach on the face recognition problem and show that it outperforms the conventional HTM approach.
AB - Hierarchical temporal memory (HTM) is a neuromorphic algorithm that emulates sparsity, hierarchy and modularity resembling the working principles of neocortex. Feature encoding is an important step to create sparse binary patterns. This sparsity is introduced by the binary weights and random weight assignment in the initialization stage of the HTM. We propose the alternative deterministic method for the HTM initialization stage, which connects the HTM weights to the input data and preserves natural sparsity of the input information. Further, we introduce the hardware implementation of the deterministic approach and compare it to the traditional HTM and existing hardware implementation. We test the proposed approach on the face recognition problem and show that it outperforms the conventional HTM approach.
KW - Analog circuits
KW - Hierarchical temporal memory
KW - Memristors
KW - Rule based approach
KW - Spatial Pooler
UR - http://www.scopus.com/inward/record.url?scp=85044018287&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85044018287&partnerID=8YFLogxK
U2 - 10.1007/s10470-018-1161-1
DO - 10.1007/s10470-018-1161-1
M3 - Article
AN - SCOPUS:85044018287
SP - 1
EP - 9
JO - Analog Integrated Circuits and Signal Processing
JF - Analog Integrated Circuits and Signal Processing
SN - 0925-1030
ER -