FPGA FFT implementation

S. O. Churayev, B. T. Matkarimov

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We consider FPGA design flow with C/C++ to Verilog translation and verification and report on FPGA implementation of fast Fourier transform and Wiener filter for noise reduction of speech signals on Xilinx Virtex-4.

Original languageEnglish
Title of host publicationProceedings of IEEE East-West Design and Test Symposium, EWDTS'10
Pages183-185
Number of pages3
DOIs
Publication statusPublished - Dec 1 2010
EventIEEE East-West Design and Test Symposium, EWDTS'10 - St. Petersburg, Russian Federation
Duration: Sep 17 2010Sep 20 2010

Publication series

NameProceedings of IEEE East-West Design and Test Symposium, EWDTS'10

Other

OtherIEEE East-West Design and Test Symposium, EWDTS'10
CountryRussian Federation
CitySt. Petersburg
Period9/17/109/20/10

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture

Fingerprint Dive into the research topics of 'FPGA FFT implementation'. Together they form a unique fingerprint.

Cite this