Hierarchical Temporal Memory Using Memristor Networks: A Survey

Olga Krestinskaya, Irina Dolzhikova, Alex Pappachen James

Research output: Contribution to journalArticlepeer-review

14 Citations (Scopus)


This paper presents a survey of the currently available hardware designs for implementation of the human cortex inspired algorithm, Hierarchical Temporal Memory (HTM). In this review, we focus on the state-of-the-art advances of memristive HTM implementation and related HTM applications. With the advent of edge computing, HTM can be a potential algorithm to implement on-chip near sensor data processing. The comparison of analog memristive circuit implementations with the digital and mixed-signal solutions is provided. The advantages of memristive HTM over digital implementations against performance metrics such as processing speed, reduced on-chip area, and power dissipation are discussed. The limitations and open problems concerning the memristive HTM, such as the design scalability, sneak currents, leakage, parasitic effects, lack of the analog learning circuits implementations, and unreliability of the memristive devices integrated with CMOS circuits are also discussed.

Original languageEnglish
Article number8471012
Pages (from-to)380-395
Number of pages16
JournalIEEE Transactions on Emerging Topics in Computational Intelligence
Issue number5
Publication statusPublished - Oct 2018


  • crossbar
  • Hierarchical temporal memory
  • memristor
  • spatial pooler
  • spin-neuron
  • temporal memory

ASJC Scopus subject areas

  • Artificial Intelligence
  • Computer Science Applications
  • Computational Mathematics
  • Control and Optimization

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