HTM Spatial Pooler With Memristor Crossbar Circuits for Sparse Biometric Recognition

Alex Pappachen James; Irina Fedorova; Timur Ibrayev; Dhireesha Kudithipudi

doi:10.1109/TBCAS.2016.2641983

HTM Spatial Pooler With Memristor Crossbar Circuits for Sparse Biometric Recognition

Alex Pappachen James, Irina Fedorova, Timur Ibrayev, Dhireesha Kudithipudi

Department of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

32 Citations (Scopus)

Abstract

Hierarchical Temporal Memory (HTM) is an online machine learning algorithm that emulates the neo-cortex. The development of a scalable on-chip HTM architecture is an open research area. The two core substructures of HTM are spatial pooler and temporal memory. In this work, we propose a new Spatial Pooler circuit design with parallel memristive crossbar arrays for the 2D columns. The proposed design was validated on two different benchmark datasets, face recognition, and speech recognition. The circuits are simulated and analyzed using a practical memristor device model and 0.18 μm IBM CMOS technology model. The databases AR, YALE, ORL, and UFI, are used to test the performance of the design in face recognition. TIMIT dataset is used for the speech recognition.

Original language	English
Journal	IEEE Transactions on Biomedical Circuits and Systems
DOIs	https://doi.org/10.1109/TBCAS.2016.2641983
Publication status	Accepted/In press - Mar 1 2017

ASJC Scopus subject areas

Biomedical Engineering
Electrical and Electronic Engineering

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@article{1d8a83b30b9849cdaaec8a8e4ad050c5,

title = "HTM Spatial Pooler With Memristor Crossbar Circuits for Sparse Biometric Recognition",

abstract = "Hierarchical Temporal Memory (HTM) is an online machine learning algorithm that emulates the neo-cortex. The development of a scalable on-chip HTM architecture is an open research area. The two core substructures of HTM are spatial pooler and temporal memory. In this work, we propose a new Spatial Pooler circuit design with parallel memristive crossbar arrays for the 2D columns. The proposed design was validated on two different benchmark datasets, face recognition, and speech recognition. The circuits are simulated and analyzed using a practical memristor device model and 0.18 μm IBM CMOS technology model. The databases AR, YALE, ORL, and UFI, are used to test the performance of the design in face recognition. TIMIT dataset is used for the speech recognition.",

author = "James, {Alex Pappachen} and Irina Fedorova and Timur Ibrayev and Dhireesha Kudithipudi",

year = "2017",

month = mar,

day = "1",

doi = "10.1109/TBCAS.2016.2641983",

language = "English",

journal = "IEEE Transactions on Biomedical Circuits and Systems",

issn = "1932-4545",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - JOUR

T1 - HTM Spatial Pooler With Memristor Crossbar Circuits for Sparse Biometric Recognition

AU - James, Alex Pappachen

AU - Fedorova, Irina

AU - Ibrayev, Timur

AU - Kudithipudi, Dhireesha

PY - 2017/3/1

Y1 - 2017/3/1

N2 - Hierarchical Temporal Memory (HTM) is an online machine learning algorithm that emulates the neo-cortex. The development of a scalable on-chip HTM architecture is an open research area. The two core substructures of HTM are spatial pooler and temporal memory. In this work, we propose a new Spatial Pooler circuit design with parallel memristive crossbar arrays for the 2D columns. The proposed design was validated on two different benchmark datasets, face recognition, and speech recognition. The circuits are simulated and analyzed using a practical memristor device model and 0.18 μm IBM CMOS technology model. The databases AR, YALE, ORL, and UFI, are used to test the performance of the design in face recognition. TIMIT dataset is used for the speech recognition.

AB - Hierarchical Temporal Memory (HTM) is an online machine learning algorithm that emulates the neo-cortex. The development of a scalable on-chip HTM architecture is an open research area. The two core substructures of HTM are spatial pooler and temporal memory. In this work, we propose a new Spatial Pooler circuit design with parallel memristive crossbar arrays for the 2D columns. The proposed design was validated on two different benchmark datasets, face recognition, and speech recognition. The circuits are simulated and analyzed using a practical memristor device model and 0.18 μm IBM CMOS technology model. The databases AR, YALE, ORL, and UFI, are used to test the performance of the design in face recognition. TIMIT dataset is used for the speech recognition.

UR - http://www.scopus.com/inward/record.url?scp=85016485428&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85016485428&partnerID=8YFLogxK

U2 - 10.1109/TBCAS.2016.2641983

DO - 10.1109/TBCAS.2016.2641983

M3 - Article

C2 - 28362614

AN - SCOPUS:85016485428

JO - IEEE Transactions on Biomedical Circuits and Systems

JF - IEEE Transactions on Biomedical Circuits and Systems

SN - 1932-4545

ER -