InAlAs/InGaAs Heterostructure FET’s Processed with Selective Reactive-Ion-Etching Gate-Recess Technology

Sambhu Agarwala; K. Nummila; Ilesanmi Adesida; Catherine Caneau; Rajaram Bhat

doi:10.1109/55.244718

InAlAs/InGaAs Heterostructure FET’s Processed with Selective Reactive-Ion-Etching Gate-Recess Technology

Sambhu Agarwala, K. Nummila, Ilesanmi Adesida, Catherine Caneau, Rajaram Bhat

Research output: Contribution to journal › Article

15 Citations (Scopus)

Abstract

A newly developed highly selective reactive-ion-etching process based on HBr plasma has been applied as a gate-recess technique in the fabrication of InAlAs/InGaAs heterostructure FET’s. A typical 0.75-μm gate-length transistor exhibited a threshold voltage of —1.0 V, a maximum extrinsic transconductance of 600 mS/mm, an extrinsic current-gain cutoff frequency of 37 GHz, and a maximum frequency of oscillation of 90 GHz. These dc and RF device parameters compare favorably with that of a corresponding device gate-recessed with a selective wet-etching technique.

Original language	English
Pages (from-to)	425-427
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	14
Issue number	9
DOIs	https://doi.org/10.1109/55.244718
Publication status	Published - 1993
Externally published	Yes

Fingerprint

Gates (transistor)

Wet etching

Reactive ion etching

Cutoff frequency

Transconductance

Field effect transistors

Threshold voltage

Heterojunctions

Transistors

Plasmas

Fabrication

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

Cite this

Agarwala, S., Nummila, K., Adesida, I., Caneau, C., & Bhat, R. (1993). InAlAs/InGaAs Heterostructure FET’s Processed with Selective Reactive-Ion-Etching Gate-Recess Technology. IEEE Electron Device Letters, 14(9), 425-427. https://doi.org/10.1109/55.244718

InAlAs/InGaAs Heterostructure FET’s Processed with Selective Reactive-Ion-Etching Gate-Recess Technology. / Agarwala, Sambhu; Nummila, K.; Adesida, Ilesanmi; Caneau, Catherine; Bhat, Rajaram.

In: IEEE Electron Device Letters, Vol. 14, No. 9, 1993, p. 425-427.

Research output: Contribution to journal › Article

Agarwala, S, Nummila, K, Adesida, I, Caneau, C & Bhat, R 1993, 'InAlAs/InGaAs Heterostructure FET’s Processed with Selective Reactive-Ion-Etching Gate-Recess Technology', IEEE Electron Device Letters, vol. 14, no. 9, pp. 425-427. https://doi.org/10.1109/55.244718

Agarwala S, Nummila K, Adesida I, Caneau C, Bhat R. InAlAs/InGaAs Heterostructure FET’s Processed with Selective Reactive-Ion-Etching Gate-Recess Technology. IEEE Electron Device Letters. 1993;14(9):425-427. https://doi.org/10.1109/55.244718

Agarwala, Sambhu ; Nummila, K. ; Adesida, Ilesanmi ; Caneau, Catherine ; Bhat, Rajaram. / InAlAs/InGaAs Heterostructure FET’s Processed with Selective Reactive-Ion-Etching Gate-Recess Technology. In: IEEE Electron Device Letters. 1993 ; Vol. 14, No. 9. pp. 425-427.

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Access to Document

10.1109/55.244718