InAlAs/InGaAs Heterostructure FET’s Processed with Selective Reactive-Ion-Etching Gate-Recess Technology

Sambhu Agarwala; K. Nummila; Ilesanmi Adesida; Catherine Caneau; Rajaram Bhat

doi:10.1109/55.244718

InAlAs/InGaAs Heterostructure FET’s Processed with Selective Reactive-Ion-Etching Gate-Recess Technology

Sambhu Agarwala, K. Nummila, Ilesanmi Adesida, Catherine Caneau, Rajaram Bhat

Research output: Contribution to journal › Article › peer-review

15 Citations (Scopus)

Abstract

A newly developed highly selective reactive-ion-etching process based on HBr plasma has been applied as a gate-recess technique in the fabrication of InAlAs/InGaAs heterostructure FET’s. A typical 0.75-μm gate-length transistor exhibited a threshold voltage of —1.0 V, a maximum extrinsic transconductance of 600 mS/mm, an extrinsic current-gain cutoff frequency of 37 GHz, and a maximum frequency of oscillation of 90 GHz. These dc and RF device parameters compare favorably with that of a corresponding device gate-recessed with a selective wet-etching technique.

Original language	English
Pages (from-to)	425-427
Number of pages	3
Journal	IEEE Electron Device Letters
Volume	14
Issue number	9
DOIs	https://doi.org/10.1109/55.244718
Publication status	Published - Sep 1993
Externally published	Yes

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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title = "InAlAs/InGaAs Heterostructure FET{\textquoteright}s Processed with Selective Reactive-Ion-Etching Gate-Recess Technology",

abstract = "A newly developed highly selective reactive-ion-etching process based on HBr plasma has been applied as a gate-recess technique in the fabrication of InAlAs/InGaAs heterostructure FET{\textquoteright}s. A typical 0.75-μm gate-length transistor exhibited a threshold voltage of —1.0 V, a maximum extrinsic transconductance of 600 mS/mm, an extrinsic current-gain cutoff frequency of 37 GHz, and a maximum frequency of oscillation of 90 GHz. These dc and RF device parameters compare favorably with that of a corresponding device gate-recessed with a selective wet-etching technique.",

author = "Sambhu Agarwala and K. Nummila and Ilesanmi Adesida and Catherine Caneau and Rajaram Bhat",

note = "Funding Information: Manuscript received March 29, 1993; revised June IO, 1993. This work was supported at the University of Illinois by NSF Grant ECD 89-43166, JSEP Grant N00014-90-J-1270, NSF Grant 92-02294, and URI Grant N00014-92-J-1519. S. Agarwala, K. Nummila, and I. Adesida are with the Center for Compound Semiconductor Microelectronics, Coordinated Science Laboratory, Beckman Institute, and Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, IL 61801. C. Caneau and R. Bhat are with Bell Communication Research, Red Bank, NJ 07701. IEEE Log Number 9211378.",

year = "1993",

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doi = "10.1109/55.244718",

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volume = "14",

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AU - Agarwala, Sambhu

AU - Nummila, K.

AU - Adesida, Ilesanmi

AU - Caneau, Catherine

AU - Bhat, Rajaram

N1 - Funding Information: Manuscript received March 29, 1993; revised June IO, 1993. This work was supported at the University of Illinois by NSF Grant ECD 89-43166, JSEP Grant N00014-90-J-1270, NSF Grant 92-02294, and URI Grant N00014-92-J-1519. S. Agarwala, K. Nummila, and I. Adesida are with the Center for Compound Semiconductor Microelectronics, Coordinated Science Laboratory, Beckman Institute, and Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, IL 61801. C. Caneau and R. Bhat are with Bell Communication Research, Red Bank, NJ 07701. IEEE Log Number 9211378.

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InAlAs/InGaAs Heterostructure FET’s Processed with Selective Reactive-Ion-Etching Gate-Recess Technology

Abstract

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