Information-preserving logic based on logical reversibility to reduce the memory data transfer bottleneck and heat dissipation

Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

We present an approach to the cache bottleneck problem using reversible logic circuits. The high traffic between the cache and the main memory in current systems considerably slows down the performance of the general information processing unit (IPU). Moreover this high traffic has the consequence of high heat generation in VLSI elements such as the CPU or dedicated processors. Thus the reduction in use or complete removal of the cache memory could be beneficial to current processors architecture. We present a model where the IPU is designed as a logically reversible circuit. This allows one to reduce the cachememory traffic because data can be recovered using the output of the current processing. We illustrate the implementation of the approach by providing a design of an adiabatic reversible Toffoli gate with a power consumption equivalent to a classical adiabatic circuit. With these approaches, the cache-memory bottleneck and heat dissipation can potentially be reduced even by using only logically reversible circuit implementation.

Original languageEnglish
Title of host publicationProceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011
Pages131-138
Number of pages8
DOIs
Publication statusPublished - 2011
Externally publishedYes
Event41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011 - Tuusula, Finland
Duration: May 23 2011May 25 2011

Other

Other41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011
CountryFinland
CityTuusula
Period5/23/115/25/11

Fingerprint

Reversibility
Data Transfer
Data transfer
Heat losses
Cache memory
Dissipation
Heat
Logic
Data storage equipment
Program processors
Networks (circuits)
Traffic
Information Processing
Cache
Logic circuits
Heat generation
Reversible Logic
Bottleneck Problem
Unit
Electric power utilization

Keywords

  • cache replacement algorithms
  • information preserving logic
  • reversible circuits

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Applied Mathematics

Cite this

Lukac, M., Shuai, B., Kameyama, M., & Miller, D. M. (2011). Information-preserving logic based on logical reversibility to reduce the memory data transfer bottleneck and heat dissipation. In Proceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011 (pp. 131-138). [5954221] https://doi.org/10.1109/ISMVL.2011.43

Information-preserving logic based on logical reversibility to reduce the memory data transfer bottleneck and heat dissipation. / Lukac, Martin; Shuai, Ben; Kameyama, Michitaka; Miller, D. Michael.

Proceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011. 2011. p. 131-138 5954221.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lukac, M, Shuai, B, Kameyama, M & Miller, DM 2011, Information-preserving logic based on logical reversibility to reduce the memory data transfer bottleneck and heat dissipation. in Proceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011., 5954221, pp. 131-138, 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011, Tuusula, Finland, 5/23/11. https://doi.org/10.1109/ISMVL.2011.43
Lukac M, Shuai B, Kameyama M, Miller DM. Information-preserving logic based on logical reversibility to reduce the memory data transfer bottleneck and heat dissipation. In Proceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011. 2011. p. 131-138. 5954221 https://doi.org/10.1109/ISMVL.2011.43
Lukac, Martin ; Shuai, Ben ; Kameyama, Michitaka ; Miller, D. Michael. / Information-preserving logic based on logical reversibility to reduce the memory data transfer bottleneck and heat dissipation. Proceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011. 2011. pp. 131-138
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