Abstract
We present an approach to the cache bottleneck problem using reversible logic circuits. The high traffic between the cache and the main memory in current systems considerably slows down the performance of the general information processing unit (IPU). Moreover this high traffic has the consequence of high heat generation in VLSI elements such as the CPU or dedicated processors. Thus the reduction in use or complete removal of the cache memory could be beneficial to current processors architecture. We present a model where the IPU is designed as a logically reversible circuit. This allows one to reduce the cachememory traffic because data can be recovered using the output of the current processing. We illustrate the implementation of the approach by providing a design of an adiabatic reversible Toffoli gate with a power consumption equivalent to a classical adiabatic circuit. With these approaches, the cache-memory bottleneck and heat dissipation can potentially be reduced even by using only logically reversible circuit implementation.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011 |
| Pages | 131-138 |
| Number of pages | 8 |
| DOIs | |
| Publication status | Published - 2011 |
| Externally published | Yes |
| Event | 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011 - Tuusula, Finland Duration: May 23 2011 → May 25 2011 |
Other
| Other | 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011 |
|---|---|
| Country | Finland |
| City | Tuusula |
| Period | 5/23/11 → 5/25/11 |
Fingerprint
Keywords
- cache replacement algorithms
- information preserving logic
- reversible circuits
ASJC Scopus subject areas
- Computational Theory and Mathematics
- Applied Mathematics
Cite this
Information-preserving logic based on logical reversibility to reduce the memory data transfer bottleneck and heat dissipation. / Lukac, Martin; Shuai, Ben; Kameyama, Michitaka; Miller, D. Michael.
Proceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011. 2011. p. 131-138 5954221.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Information-preserving logic based on logical reversibility to reduce the memory data transfer bottleneck and heat dissipation
AU - Lukac, Martin
AU - Shuai, Ben
AU - Kameyama, Michitaka
AU - Miller, D. Michael
PY - 2011
Y1 - 2011
N2 - We present an approach to the cache bottleneck problem using reversible logic circuits. The high traffic between the cache and the main memory in current systems considerably slows down the performance of the general information processing unit (IPU). Moreover this high traffic has the consequence of high heat generation in VLSI elements such as the CPU or dedicated processors. Thus the reduction in use or complete removal of the cache memory could be beneficial to current processors architecture. We present a model where the IPU is designed as a logically reversible circuit. This allows one to reduce the cachememory traffic because data can be recovered using the output of the current processing. We illustrate the implementation of the approach by providing a design of an adiabatic reversible Toffoli gate with a power consumption equivalent to a classical adiabatic circuit. With these approaches, the cache-memory bottleneck and heat dissipation can potentially be reduced even by using only logically reversible circuit implementation.
AB - We present an approach to the cache bottleneck problem using reversible logic circuits. The high traffic between the cache and the main memory in current systems considerably slows down the performance of the general information processing unit (IPU). Moreover this high traffic has the consequence of high heat generation in VLSI elements such as the CPU or dedicated processors. Thus the reduction in use or complete removal of the cache memory could be beneficial to current processors architecture. We present a model where the IPU is designed as a logically reversible circuit. This allows one to reduce the cachememory traffic because data can be recovered using the output of the current processing. We illustrate the implementation of the approach by providing a design of an adiabatic reversible Toffoli gate with a power consumption equivalent to a classical adiabatic circuit. With these approaches, the cache-memory bottleneck and heat dissipation can potentially be reduced even by using only logically reversible circuit implementation.
KW - cache replacement algorithms
KW - information preserving logic
KW - reversible circuits
UR - http://www.scopus.com/inward/record.url?scp=80051623184&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80051623184&partnerID=8YFLogxK
U2 - 10.1109/ISMVL.2011.43
DO - 10.1109/ISMVL.2011.43
M3 - Conference contribution
AN - SCOPUS:80051623184
SN - 9780769544052
SP - 131
EP - 138
BT - Proceedings - 41st IEEE International Symposium on Multiple-Valued Logic, ISMVL 2011
ER -