InP-based HEMTs for high speed, low power circuit applications

I. Adesida, A. Mahajan, G. Cueva

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Processes for the monolithic integration of enhancement- and depletion-mode HEMTs (E/D-HEMTs) in the lattice matched InP material system are described. Using the buried Pt gate technology, 0.3 μm gate-length E-HEMTs exhibiting a threshold voltage of +167 mV and a maximum extrinsic transconductance, gmext, of 700 mS/mm are demonstrated. D-HEMTs with corresponding device parameters of -443 mV and 462 mS/mm are presented. Unity current gain cut-off frequencies of over 95 GHz were obtained for these devices. Implementation of a divide-by-four prescaler in the direct coupled FET logic technology based on E- and D-HEMTs is demonstrated.

Original languageEnglish
Pages (from-to)579-582
Number of pages4
JournalInternational Conference on Solid-State and Integrated Circuit Technology Proceedings
Publication statusPublished - 1998
Externally publishedYes

Fingerprint

High electron mobility transistors
Networks (circuits)
Cutoff frequency
Transconductance
Field effect transistors
Threshold voltage

ASJC Scopus subject areas

  • Engineering(all)

Cite this

@article{0e971e4c634544b990522fcd08f5e22d,
title = "InP-based HEMTs for high speed, low power circuit applications",
abstract = "Processes for the monolithic integration of enhancement- and depletion-mode HEMTs (E/D-HEMTs) in the lattice matched InP material system are described. Using the buried Pt gate technology, 0.3 μm gate-length E-HEMTs exhibiting a threshold voltage of +167 mV and a maximum extrinsic transconductance, gmext, of 700 mS/mm are demonstrated. D-HEMTs with corresponding device parameters of -443 mV and 462 mS/mm are presented. Unity current gain cut-off frequencies of over 95 GHz were obtained for these devices. Implementation of a divide-by-four prescaler in the direct coupled FET logic technology based on E- and D-HEMTs is demonstrated.",
author = "I. Adesida and A. Mahajan and G. Cueva",
year = "1998",
language = "English",
pages = "579--582",
journal = "International Conference on Solid-State and Integrated Circuit Technology Proceedings",

}

TY - JOUR

T1 - InP-based HEMTs for high speed, low power circuit applications

AU - Adesida, I.

AU - Mahajan, A.

AU - Cueva, G.

PY - 1998

Y1 - 1998

N2 - Processes for the monolithic integration of enhancement- and depletion-mode HEMTs (E/D-HEMTs) in the lattice matched InP material system are described. Using the buried Pt gate technology, 0.3 μm gate-length E-HEMTs exhibiting a threshold voltage of +167 mV and a maximum extrinsic transconductance, gmext, of 700 mS/mm are demonstrated. D-HEMTs with corresponding device parameters of -443 mV and 462 mS/mm are presented. Unity current gain cut-off frequencies of over 95 GHz were obtained for these devices. Implementation of a divide-by-four prescaler in the direct coupled FET logic technology based on E- and D-HEMTs is demonstrated.

AB - Processes for the monolithic integration of enhancement- and depletion-mode HEMTs (E/D-HEMTs) in the lattice matched InP material system are described. Using the buried Pt gate technology, 0.3 μm gate-length E-HEMTs exhibiting a threshold voltage of +167 mV and a maximum extrinsic transconductance, gmext, of 700 mS/mm are demonstrated. D-HEMTs with corresponding device parameters of -443 mV and 462 mS/mm are presented. Unity current gain cut-off frequencies of over 95 GHz were obtained for these devices. Implementation of a divide-by-four prescaler in the direct coupled FET logic technology based on E- and D-HEMTs is demonstrated.

UR - http://www.scopus.com/inward/record.url?scp=0032226784&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032226784&partnerID=8YFLogxK

M3 - Article

SP - 579

EP - 582

JO - International Conference on Solid-State and Integrated Circuit Technology Proceedings

JF - International Conference on Solid-State and Integrated Circuit Technology Proceedings

ER -