Processes for the monolithic integration of enhancement- and depletion-mode HEMTs (E/D-HEMTs) in the lattice matched InP material system are described. Using the buried Pt gate technology, 0.3 μm gate-length E-HEMTs exhibiting a threshold voltage of +167 mV and a maximum extrinsic transconductance, gmext, of 700 mS/mm are demonstrated. D-HEMTs with corresponding device parameters of -443 mV and 462 mS/mm are presented. Unity current gain cut-off frequencies of over 95 GHz were obtained for these devices. Implementation of a divide-by-four prescaler in the direct coupled FET logic technology based on E- and D-HEMTs is demonstrated.
|Number of pages||4|
|Publication status||Published - Dec 1 1998|
|Event||Proceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology - Beijing, China|
Duration: Oct 21 1998 → Oct 23 1998
|Conference||Proceedings of the 1998 5th International Conference on Solid-State and Integrated Circuit Technology|
|Period||10/21/98 → 10/23/98|
ASJC Scopus subject areas