Integrated optical receiver module with demultiplexer for chip-to-chip optical interconnects

Nga T.H. Nguyen; Ikechi Augustine Ukaegbu; Jamshid Sangirov; Hyo Hoon Park

doi:10.1117/12.2541230

Integrated optical receiver module with demultiplexer for chip-to-chip optical interconnects

Nga T.H. Nguyen, Ikechi Augustine Ukaegbu, Jamshid Sangirov, Hyo Hoon Park

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, an integrated optical receiver module with demultiplexer chip-to-chip optical interconnects is proposed. The receiver and demultiplexer (demux) were realized on a single chip in a 0.18 μm TSMC CMOS technology. The topology uses a 1:2 for the demux while the receiver (Rx) module consists of transimpedance amplifier (TIA) and a limiting amplifier (LA). The receiver achieved a gain of 90 dBω and a 3-dB bandwidth of 4.5 GHz. Clear eye diagrams were observed with a voltage swing of 375 mVpp up to 2.5 Gbps output from the Rx-Demux at 5 Gbps input signal. The integrated chip occupies an area of 594x1089 μm² with power consumptions of 122 mA under a 1.8 V power supply This solution could be applied to CPU/memory interface where bidirectional signaling is required.

Original language	English
Title of host publication	Optical Interconnects XX
Editors	Henning Schroder, Ray T. Chen
Publisher	SPIE
ISBN (Electronic)	9781510633353
DOIs	https://doi.org/10.1117/12.2541230
Publication status	Published - 2020
Event	Optical Interconnects XX 2020 - San Francisco, United States Duration: Feb 4 2020 → Feb 6 2020

Publication series

Name	Proceedings of SPIE - The International Society for Optical Engineering
Volume	11286
ISSN (Print)	0277-786X
ISSN (Electronic)	1996-756X

Conference

Conference	Optical Interconnects XX 2020
Country	United States
City	San Francisco
Period	2/4/20 → 2/6/20

Keywords

Demultiplexer
Limiting amplifier
Optical interconnects
Receiver

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Computer Science Applications
Applied Mathematics
Electrical and Electronic Engineering

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Integrated optical receiver module with demultiplexer for chip-to-chip optical interconnects. / Nguyen, Nga T.H.; Ukaegbu, Ikechi Augustine; Sangirov, Jamshid; Park, Hyo Hoon.

Optical Interconnects XX. ed. / Henning Schroder; Ray T. Chen. SPIE, 2020. 112860S (Proceedings of SPIE - The International Society for Optical Engineering; Vol. 11286).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nguyen, NTH, Ukaegbu, IA, Sangirov, J & Park, HH 2020, Integrated optical receiver module with demultiplexer for chip-to-chip optical interconnects. in H Schroder & RT Chen (eds), Optical Interconnects XX., 112860S, Proceedings of SPIE - The International Society for Optical Engineering, vol. 11286, SPIE, Optical Interconnects XX 2020, San Francisco, United States, 2/4/20. https://doi.org/10.1117/12.2541230

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PY - 2020

Y1 - 2020

N2 - In this paper, an integrated optical receiver module with demultiplexer chip-to-chip optical interconnects is proposed. The receiver and demultiplexer (demux) were realized on a single chip in a 0.18 μm TSMC CMOS technology. The topology uses a 1:2 for the demux while the receiver (Rx) module consists of transimpedance amplifier (TIA) and a limiting amplifier (LA). The receiver achieved a gain of 90 dBω and a 3-dB bandwidth of 4.5 GHz. Clear eye diagrams were observed with a voltage swing of 375 mVpp up to 2.5 Gbps output from the Rx-Demux at 5 Gbps input signal. The integrated chip occupies an area of 594x1089 μm2 with power consumptions of 122 mA under a 1.8 V power supply This solution could be applied to CPU/memory interface where bidirectional signaling is required.

AB - In this paper, an integrated optical receiver module with demultiplexer chip-to-chip optical interconnects is proposed. The receiver and demultiplexer (demux) were realized on a single chip in a 0.18 μm TSMC CMOS technology. The topology uses a 1:2 for the demux while the receiver (Rx) module consists of transimpedance amplifier (TIA) and a limiting amplifier (LA). The receiver achieved a gain of 90 dBω and a 3-dB bandwidth of 4.5 GHz. Clear eye diagrams were observed with a voltage swing of 375 mVpp up to 2.5 Gbps output from the Rx-Demux at 5 Gbps input signal. The integrated chip occupies an area of 594x1089 μm2 with power consumptions of 122 mA under a 1.8 V power supply This solution could be applied to CPU/memory interface where bidirectional signaling is required.

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KW - Limiting amplifier

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Integrated optical receiver module with demultiplexer for chip-to-chip optical interconnects

Abstract

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Keywords

ASJC Scopus subject areas

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