Low power High-Speed SerDes with New Dynamic Latch and Flip-Flop for Optical Interconnect in 180 nm CMOS Technology

Jamshid Sangirov, Ikechi Augustine Ukaegbu, Tae-Woo Lee, Mu-Hee Cho, Hyo-Hoon Park

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We propose a new dynamic D-latch for low-power high-speed SerDes in chip-to-chip optical interconnect. The overall SerDes circuit uses 3.6 times less number of transistors, with smaller SerDes occupying 50% less area, compared to the previous works. The SerDes operates up to 10 Gbps data rate, and the power consumption is 49.3 mW at 1.8 V, which is 30 % less power.
Original languageEnglish
Title of host publicationOptoelectronic Interconnects and Component Integration XI, 7944
PublisherSPIE
PagesV-1 - V-8
Number of pages79440
Publication statusPublished - Jan 18 2011

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Optical interconnects
Flip flop circuits
Transistors
Electric power utilization
Networks (circuits)

Cite this

Sangirov, J., Ukaegbu, I. A., Lee, T-W., Cho, M-H., & Park, H-H. (2011). Low power High-Speed SerDes with New Dynamic Latch and Flip-Flop for Optical Interconnect in 180 nm CMOS Technology. In Optoelectronic Interconnects and Component Integration XI, 7944 (pp. V-1 - V-8). SPIE.

Low power High-Speed SerDes with New Dynamic Latch and Flip-Flop for Optical Interconnect in 180 nm CMOS Technology. / Sangirov, Jamshid; Ukaegbu, Ikechi Augustine; Lee, Tae-Woo; Cho, Mu-Hee; Park, Hyo-Hoon.

Optoelectronic Interconnects and Component Integration XI, 7944. SPIE, 2011. p. V-1 - V-8.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sangirov, J, Ukaegbu, IA, Lee, T-W, Cho, M-H & Park, H-H 2011, Low power High-Speed SerDes with New Dynamic Latch and Flip-Flop for Optical Interconnect in 180 nm CMOS Technology. in Optoelectronic Interconnects and Component Integration XI, 7944. SPIE, pp. V-1 - V-8.
Sangirov J, Ukaegbu IA, Lee T-W, Cho M-H, Park H-H. Low power High-Speed SerDes with New Dynamic Latch and Flip-Flop for Optical Interconnect in 180 nm CMOS Technology. In Optoelectronic Interconnects and Component Integration XI, 7944. SPIE. 2011. p. V-1 - V-8
Sangirov, Jamshid ; Ukaegbu, Ikechi Augustine ; Lee, Tae-Woo ; Cho, Mu-Hee ; Park, Hyo-Hoon. / Low power High-Speed SerDes with New Dynamic Latch and Flip-Flop for Optical Interconnect in 180 nm CMOS Technology. Optoelectronic Interconnects and Component Integration XI, 7944. SPIE, 2011. pp. V-1 - V-8
@inproceedings{ebb0e56e30c143219002e10921162e3e,
title = "Low power High-Speed SerDes with New Dynamic Latch and Flip-Flop for Optical Interconnect in 180 nm CMOS Technology",
abstract = "We propose a new dynamic D-latch for low-power high-speed SerDes in chip-to-chip optical interconnect. The overall SerDes circuit uses 3.6 times less number of transistors, with smaller SerDes occupying 50{\%} less area, compared to the previous works. The SerDes operates up to 10 Gbps data rate, and the power consumption is 49.3 mW at 1.8 V, which is 30 {\%} less power.",
author = "Jamshid Sangirov and Ukaegbu, {Ikechi Augustine} and Tae-Woo Lee and Mu-Hee Cho and Hyo-Hoon Park",
year = "2011",
month = "1",
day = "18",
language = "English",
pages = "V--1 -- V--8",
booktitle = "Optoelectronic Interconnects and Component Integration XI, 7944",
publisher = "SPIE",
address = "United States",

}

TY - GEN

T1 - Low power High-Speed SerDes with New Dynamic Latch and Flip-Flop for Optical Interconnect in 180 nm CMOS Technology

AU - Sangirov, Jamshid

AU - Ukaegbu, Ikechi Augustine

AU - Lee, Tae-Woo

AU - Cho, Mu-Hee

AU - Park, Hyo-Hoon

PY - 2011/1/18

Y1 - 2011/1/18

N2 - We propose a new dynamic D-latch for low-power high-speed SerDes in chip-to-chip optical interconnect. The overall SerDes circuit uses 3.6 times less number of transistors, with smaller SerDes occupying 50% less area, compared to the previous works. The SerDes operates up to 10 Gbps data rate, and the power consumption is 49.3 mW at 1.8 V, which is 30 % less power.

AB - We propose a new dynamic D-latch for low-power high-speed SerDes in chip-to-chip optical interconnect. The overall SerDes circuit uses 3.6 times less number of transistors, with smaller SerDes occupying 50% less area, compared to the previous works. The SerDes operates up to 10 Gbps data rate, and the power consumption is 49.3 mW at 1.8 V, which is 30 % less power.

M3 - Conference contribution

SP - V-1 - V-8

BT - Optoelectronic Interconnects and Component Integration XI, 7944

PB - SPIE

ER -