Low power High-Speed SerDes with New Dynamic Latch and Flip-Flop for Optical Interconnect in 180 nm CMOS Technology

Jamshid Sangirov; Ikechi Augustine Ukaegbu; Tae-Woo Lee; Mu-Hee Cho; Hyo-Hoon Park

Low power High-Speed SerDes with New Dynamic Latch and Flip-Flop for Optical Interconnect in 180 nm CMOS Technology

Jamshid Sangirov, Ikechi Augustine Ukaegbu, Tae-Woo Lee, Mu-Hee Cho, Hyo-Hoon Park

School of Engineering and Digital Sciences

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

We propose a new dynamic D-latch for low-power high-speed SerDes in chip-to-chip optical interconnect. The overall SerDes circuit uses 3.6 times less number of transistors, with smaller SerDes occupying 50% less area, compared to the previous works. The SerDes operates up to 10 Gbps data rate, and the power consumption is 49.3 mW at 1.8 V, which is 30 % less power.

Original language	English
Title of host publication	Optoelectronic Interconnects and Component Integration XI, 7944
Publisher	SPIE
Pages	V-1 - V-8
Number of pages	79440
Publication status	Published - Jan 18 2011

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Low power High-Speed SerDes with New Dynamic Latch and Flip-Flop for Optical Interconnect in 180 nm CMOS Technology. / Sangirov, Jamshid; Ukaegbu, Ikechi Augustine; Lee, Tae-Woo; Cho, Mu-Hee; Park, Hyo-Hoon.

Optoelectronic Interconnects and Component Integration XI, 7944. SPIE, 2011. p. V-1 - V-8.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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abstract = "We propose a new dynamic D-latch for low-power high-speed SerDes in chip-to-chip optical interconnect. The overall SerDes circuit uses 3.6 times less number of transistors, with smaller SerDes occupying 50% less area, compared to the previous works. The SerDes operates up to 10 Gbps data rate, and the power consumption is 49.3 mW at 1.8 V, which is 30 % less power.",

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AU - Cho, Mu-Hee

AU - Park, Hyo-Hoon

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AB - We propose a new dynamic D-latch for low-power high-speed SerDes in chip-to-chip optical interconnect. The overall SerDes circuit uses 3.6 times less number of transistors, with smaller SerDes occupying 50% less area, compared to the previous works. The SerDes operates up to 10 Gbps data rate, and the power consumption is 49.3 mW at 1.8 V, which is 30 % less power.

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