Abstract
We propose a new dynamic D-latch for low-power high-speed SerDes in chip-to-chip optical interconnect. The overall SerDes circuit uses 3.6 times less number of transistors, with smaller SerDes occupying 50% less area, compared to the previous works. The SerDes operates up to 10 Gbps data rate, and the power consumption is 49.3 mW at 1.8 V, which is 30 % less power.
Original language | English |
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Title of host publication | Optoelectronic Interconnects and Component Integration XI, 7944 |
Publisher | SPIE |
Pages | V-1 - V-8 |
Number of pages | 79440 |
Publication status | Published - Jan 18 2011 |