Low power High-Speed SerDes with New Dynamic Latch and Flip-Flop for Optical Interconnect in 180 nm CMOS Technology

Jamshid Sangirov, Ikechi Augustine Ukaegbu, Tae-Woo Lee, Mu-Hee Cho, Hyo-Hoon Park

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We propose a new dynamic D-latch for low-power high-speed SerDes in chip-to-chip optical interconnect. The overall SerDes circuit uses 3.6 times less number of transistors, with smaller SerDes occupying 50% less area, compared to the previous works. The SerDes operates up to 10 Gbps data rate, and the power consumption is 49.3 mW at 1.8 V, which is 30 % less power.
Original languageEnglish
Title of host publicationOptoelectronic Interconnects and Component Integration XI, 7944
PublisherSPIE
PagesV-1 - V-8
Number of pages79440
Publication statusPublished - Jan 18 2011

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Sangirov, J., Ukaegbu, I. A., Lee, T-W., Cho, M-H., & Park, H-H. (2011). Low power High-Speed SerDes with New Dynamic Latch and Flip-Flop for Optical Interconnect in 180 nm CMOS Technology. In Optoelectronic Interconnects and Component Integration XI, 7944 (pp. V-1 - V-8). SPIE.