Low Power Near-sensor Coarse to Fine XOR based Memristive Edge Detection

Kamilya Smagulova, Aidana Irmanova, Alex James Pappachen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose XOR based memristive edge detector circuit that is integrated into a near sensor log-linear CMOS pixel. Memristor threshold logic was used to design NAND gates, which serve as a building block for XOR gates. For validation of proposed circuit functionality hardware simulation of logic gates with a pixel pair was conducted using TSMC 0.18um technology and system-level simulation of the proposed circuit using SPICE models. The proposed method operates in low power and takes a small area on chip. The power consumption of one pixel is 1.16uW and total area 36.72 um 2 without photosensing component. The power consumption of NAND circuit is 1.11pW and total area 32.4um 2 .

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2018, ISOCC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages253-254
Number of pages2
ISBN (Electronic)9781538679609
DOIs
Publication statusPublished - Feb 22 2019
Event15th International SoC Design Conference, ISOCC 2018 - Daegu, Korea, Republic of
Duration: Nov 12 2018Nov 15 2018

Publication series

NameProceedings - International SoC Design Conference 2018, ISOCC 2018

Conference

Conference15th International SoC Design Conference, ISOCC 2018
CountryKorea, Republic of
CityDaegu
Period11/12/1811/15/18

Fingerprint

Edge detection
Pixels
NAND circuits
Sensors
Electric power utilization
Detector circuits
Threshold logic
Memristors
Logic gates
Networks (circuits)
SPICE
Hardware

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Smagulova, K., Irmanova, A., & James Pappachen, A. (2019). Low Power Near-sensor Coarse to Fine XOR based Memristive Edge Detection. In Proceedings - International SoC Design Conference 2018, ISOCC 2018 (pp. 253-254). [8649972] (Proceedings - International SoC Design Conference 2018, ISOCC 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2018.8649972

Low Power Near-sensor Coarse to Fine XOR based Memristive Edge Detection. / Smagulova, Kamilya; Irmanova, Aidana; James Pappachen, Alex.

Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 253-254 8649972 (Proceedings - International SoC Design Conference 2018, ISOCC 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Smagulova, K, Irmanova, A & James Pappachen, A 2019, Low Power Near-sensor Coarse to Fine XOR based Memristive Edge Detection. in Proceedings - International SoC Design Conference 2018, ISOCC 2018., 8649972, Proceedings - International SoC Design Conference 2018, ISOCC 2018, Institute of Electrical and Electronics Engineers Inc., pp. 253-254, 15th International SoC Design Conference, ISOCC 2018, Daegu, Korea, Republic of, 11/12/18. https://doi.org/10.1109/ISOCC.2018.8649972
Smagulova K, Irmanova A, James Pappachen A. Low Power Near-sensor Coarse to Fine XOR based Memristive Edge Detection. In Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 253-254. 8649972. (Proceedings - International SoC Design Conference 2018, ISOCC 2018). https://doi.org/10.1109/ISOCC.2018.8649972
Smagulova, Kamilya ; Irmanova, Aidana ; James Pappachen, Alex. / Low Power Near-sensor Coarse to Fine XOR based Memristive Edge Detection. Proceedings - International SoC Design Conference 2018, ISOCC 2018. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 253-254 (Proceedings - International SoC Design Conference 2018, ISOCC 2018).
@inproceedings{c7c34c69105a463a82b2354e198877e1,
title = "Low Power Near-sensor Coarse to Fine XOR based Memristive Edge Detection",
abstract = "In this paper, we propose XOR based memristive edge detector circuit that is integrated into a near sensor log-linear CMOS pixel. Memristor threshold logic was used to design NAND gates, which serve as a building block for XOR gates. For validation of proposed circuit functionality hardware simulation of logic gates with a pixel pair was conducted using TSMC 0.18um technology and system-level simulation of the proposed circuit using SPICE models. The proposed method operates in low power and takes a small area on chip. The power consumption of one pixel is 1.16uW and total area 36.72 um 2 without photosensing component. The power consumption of NAND circuit is 1.11pW and total area 32.4um 2 .",
author = "Kamilya Smagulova and Aidana Irmanova and {James Pappachen}, Alex",
year = "2019",
month = "2",
day = "22",
doi = "10.1109/ISOCC.2018.8649972",
language = "English",
series = "Proceedings - International SoC Design Conference 2018, ISOCC 2018",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "253--254",
booktitle = "Proceedings - International SoC Design Conference 2018, ISOCC 2018",
address = "United States",

}

TY - GEN

T1 - Low Power Near-sensor Coarse to Fine XOR based Memristive Edge Detection

AU - Smagulova, Kamilya

AU - Irmanova, Aidana

AU - James Pappachen, Alex

PY - 2019/2/22

Y1 - 2019/2/22

N2 - In this paper, we propose XOR based memristive edge detector circuit that is integrated into a near sensor log-linear CMOS pixel. Memristor threshold logic was used to design NAND gates, which serve as a building block for XOR gates. For validation of proposed circuit functionality hardware simulation of logic gates with a pixel pair was conducted using TSMC 0.18um technology and system-level simulation of the proposed circuit using SPICE models. The proposed method operates in low power and takes a small area on chip. The power consumption of one pixel is 1.16uW and total area 36.72 um 2 without photosensing component. The power consumption of NAND circuit is 1.11pW and total area 32.4um 2 .

AB - In this paper, we propose XOR based memristive edge detector circuit that is integrated into a near sensor log-linear CMOS pixel. Memristor threshold logic was used to design NAND gates, which serve as a building block for XOR gates. For validation of proposed circuit functionality hardware simulation of logic gates with a pixel pair was conducted using TSMC 0.18um technology and system-level simulation of the proposed circuit using SPICE models. The proposed method operates in low power and takes a small area on chip. The power consumption of one pixel is 1.16uW and total area 36.72 um 2 without photosensing component. The power consumption of NAND circuit is 1.11pW and total area 32.4um 2 .

UR - http://www.scopus.com/inward/record.url?scp=85063194554&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85063194554&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2018.8649972

DO - 10.1109/ISOCC.2018.8649972

M3 - Conference contribution

T3 - Proceedings - International SoC Design Conference 2018, ISOCC 2018

SP - 253

EP - 254

BT - Proceedings - International SoC Design Conference 2018, ISOCC 2018

PB - Institute of Electrical and Electronics Engineers Inc.

ER -