Memristive non-idealities: Is there any practical implications for designing neural network chips?

Olga Krestinskaya, Aidana Irmanova, Alex James

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

The impact of device-to-device, cycle-to-cycle, and parasitic variations in memristor devices on the performance of neural network architectures is not a fully understood topic. In this paper, we present an explicit analysis of memristor variabilities and non-idealities of memristive crossbar based learning architectures. The measurements of real devices and their effects on dot product operation in a memristive crossbar is reported. The effect of these non-idealities, limited resistive levels and variabilities on the performance and reliability of two-layer Artificial Neural Network (ANN), Convolutional Neural Network (CNN) and Binary Neural Network (BNN) is analyzed and presented.

Original languageEnglish
Title of host publication2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728103976
DOIs
Publication statusPublished - Jan 1 2019
Event2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019 - Sapporo, Japan
Duration: May 26 2019May 29 2019

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
Volume2019-May
ISSN (Print)0271-4310

Conference

Conference2019 IEEE International Symposium on Circuits and Systems, ISCAS 2019
CountryJapan
CitySapporo
Period5/26/195/29/19

Keywords

  • Learning Architectures
  • Memristive Crossbar
  • Memristor
  • Variability

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Memristive non-idealities: Is there any practical implications for designing neural network chips?'. Together they form a unique fingerprint.

Cite this