Field Programmable Gate Arrays (FPGAs) belong to a class of semiconductor devices whose hardware can be changed according to our needs. The configuration data (bitstreams) of an FPGA define the functionality of the FPGA. Therefore, a user can design the hardware and change it by modifying the bitstreams for a given set of requirements. One way of doing this is using Dynamic Circuit Specialization (DCS), an FPGA implementation technique that is optimized for a parameterized design. A design is said to be parameterized if some of its inputs are infrequently changing compared to the rest. In the DCS technique, for every change in parameterized input values, a new specialized circuit is generated during run-time and the FPGA is reconfigured accordingly. The time taken to reconfigure the FPGA with a specialized circuit is called reconfiguration time and is a major overhead of the DCS technique. To reduce this overhead, we propose an efficient custom reconfiguration controller built with a simple architecture which is customized to implement DCS. Our results indicate an increase in the reconfiguration speed by ≈ 17% and the FPGA resource utilization is reduced by ≈ 50% compared to the standard Xilinx reconfiguration controller.