Minimizing reversible circuits in the 2n scheme using two and three bits patterns

Martin Lukac, Maher Hawash, Michitaka Kameyama, Marek Perkowski, Pawel Kerntopf

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper we present improvements to the cost of quantum circuits implemented with 2n-lines circuit implementation. The 2n-line circuit implementation is intended for the linear nearest neighbor quantum circuits and implements any quantum circuits in such manner that they can be directly mapped to quantum implementations. In this paper we propose a replacement strategy for 2- and 3-qubit patterns detected on the control lines. It is demonstrated that application of this strategy leads to a considerable reduction of circuit cost.

Original languageEnglish
Title of host publicationProceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages708-711
Number of pages4
ISBN (Print)9781479957934
DOIs
Publication statusPublished - Oct 16 2014
Externally publishedYes
Event17th Euromicro Conference on Digital System Design, DSD 2014 - Verona, Italy
Duration: Aug 27 2014Aug 29 2014

Other

Other17th Euromicro Conference on Digital System Design, DSD 2014
CountryItaly
CityVerona
Period8/27/148/29/14

Fingerprint

Networks (circuits)
Costs

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Information Systems
  • Hardware and Architecture

Cite this

Lukac, M., Hawash, M., Kameyama, M., Perkowski, M., & Kerntopf, P. (2014). Minimizing reversible circuits in the 2n scheme using two and three bits patterns. In Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014 (pp. 708-711). [6927319] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DSD.2014.106

Minimizing reversible circuits in the 2n scheme using two and three bits patterns. / Lukac, Martin; Hawash, Maher; Kameyama, Michitaka; Perkowski, Marek; Kerntopf, Pawel.

Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 708-711 6927319.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Lukac, M, Hawash, M, Kameyama, M, Perkowski, M & Kerntopf, P 2014, Minimizing reversible circuits in the 2n scheme using two and three bits patterns. in Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014., 6927319, Institute of Electrical and Electronics Engineers Inc., pp. 708-711, 17th Euromicro Conference on Digital System Design, DSD 2014, Verona, Italy, 8/27/14. https://doi.org/10.1109/DSD.2014.106
Lukac M, Hawash M, Kameyama M, Perkowski M, Kerntopf P. Minimizing reversible circuits in the 2n scheme using two and three bits patterns. In Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 708-711. 6927319 https://doi.org/10.1109/DSD.2014.106
Lukac, Martin ; Hawash, Maher ; Kameyama, Michitaka ; Perkowski, Marek ; Kerntopf, Pawel. / Minimizing reversible circuits in the 2n scheme using two and three bits patterns. Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 708-711
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