Minimizing reversible circuits in the 2n scheme using two and three bits patterns

Martin Lukac; Maher Hawash; Michitaka Kameyama; Marek Perkowski; Pawel Kerntopf

doi:10.1109/DSD.2014.106

Minimizing reversible circuits in the 2n scheme using two and three bits patterns

Martin Lukac, Maher Hawash, Michitaka Kameyama, Marek Perkowski, Pawel Kerntopf

Department of Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper we present improvements to the cost of quantum circuits implemented with 2n-lines circuit implementation. The 2n-line circuit implementation is intended for the linear nearest neighbor quantum circuits and implements any quantum circuits in such manner that they can be directly mapped to quantum implementations. In this paper we propose a replacement strategy for 2- and 3-qubit patterns detected on the control lines. It is demonstrated that application of this strategy leads to a considerable reduction of circuit cost.

Original language	English
Title of host publication	Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	708-711
Number of pages	4
ISBN (Electronic)	9781479957934
DOIs	https://doi.org/10.1109/DSD.2014.106
Publication status	Published - Oct 16 2014
Event	17th Euromicro Conference on Digital System Design, DSD 2014 - Verona, Italy Duration: Aug 27 2014 → Aug 29 2014

Publication series

Name	Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014

Other

Other	17th Euromicro Conference on Digital System Design, DSD 2014
Country	Italy
City	Verona
Period	8/27/14 → 8/29/14

ASJC Scopus subject areas

Control and Systems Engineering
Information Systems
Hardware and Architecture

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Lukac, M., Hawash, M., Kameyama, M., Perkowski, M., & Kerntopf, P. (2014). Minimizing reversible circuits in the 2n scheme using two and three bits patterns. In Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014 (pp. 708-711). [6927319] (Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DSD.2014.106

Minimizing reversible circuits in the 2n scheme using two and three bits patterns. / Lukac, Martin; Hawash, Maher; Kameyama, Michitaka; Perkowski, Marek; Kerntopf, Pawel.

Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014. Institute of Electrical and Electronics Engineers Inc., 2014. p. 708-711 6927319 (Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lukac, M, Hawash, M, Kameyama, M, Perkowski, M & Kerntopf, P 2014, Minimizing reversible circuits in the 2n scheme using two and three bits patterns. in Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014., 6927319, Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014, Institute of Electrical and Electronics Engineers Inc., pp. 708-711, 17th Euromicro Conference on Digital System Design, DSD 2014, Verona, Italy, 8/27/14. https://doi.org/10.1109/DSD.2014.106

Lukac M, Hawash M, Kameyama M, Perkowski M, Kerntopf P. Minimizing reversible circuits in the 2n scheme using two and three bits patterns. In Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014. Institute of Electrical and Electronics Engineers Inc. 2014. p. 708-711. 6927319. (Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014). https://doi.org/10.1109/DSD.2014.106

Lukac, Martin ; Hawash, Maher ; Kameyama, Michitaka ; Perkowski, Marek ; Kerntopf, Pawel. / Minimizing reversible circuits in the 2n scheme using two and three bits patterns. Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014. Institute of Electrical and Electronics Engineers Inc., 2014. pp. 708-711 (Proceedings - 2014 17th Euromicro Conference on Digital System Design, DSD 2014).

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Minimizing reversible circuits in the 2n scheme using two and three bits patterns

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