Multi-level memristive memory with resistive networks

Aidana Irmanova, Alex Pappachen James

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Analog memory is of great importance in neurocomputing technologies field, but still remains difficult to implement. With emergence of memristors in VLSI technologies the idea of designing scalable analog data storage elements finds its second wind. A memristor, known for its history dependent resistance levels, independently can provide blocks of binary or discrete state data storage. However, using single memristor to save the analog value is practically limited due to the device variability and implementation complexity. In this paper, we present a new design of discrete state memory cell consisting of sub-cells constructed from a memristor and its resistive network. A memristor in the sub-cells provides the storage element, while its resistive network is used for programming its resistance. Several sub-cells are then connected in parallel, resembling potential divider configuration. The output of the memory cell is the voltage resulting from distributing the input voltage among the sub-cells. Here, proposed design was programmed to obtain 10 and 27 different output levels depending on the configuration of the combined resistive networks within the sub-cell. Despite the simplicity of the circuit, this realization of multilevel memory provides increased number of output levels compared to previous designs of memory technologies based on memristors. Simulation results of proposed memory are analyzed providing explicit data on the issues of distinguishing discrete analog output levels and sensitivity of the cell to oscillations in write signal patterns.

Original languageEnglish
Title of host publication2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics
Subtitle of host publicationAdvancing Circuits and Systems Innovation for Connected World, PrimeAsia 2017 - Proceedings
PublisherIEEE Computer Society
Pages69-72
Number of pages4
Volume2017-October
ISBN (Electronic)9781538605240
ISBN (Print)9781538605240
DOIs
Publication statusPublished - Feb 2 2018
Externally publishedYes
Event2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2017 - Kuala Lumpur, Malaysia
Duration: Oct 31 2017Nov 2 2017

Publication series

NameAsia Pacific Conference on Postgraduate Research in Microelectronics and Electronics
Volume2017-October

Conference

Conference2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2017
CountryMalaysia
CityKuala Lumpur
Period10/31/1711/2/17

Keywords

  • Analog memory
  • discrete state memory
  • memristor
  • multilevel
  • neuron
  • ternary logic
  • weighted logic

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Education

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  • Cite this

    Irmanova, A., & James, A. P. (2018). Multi-level memristive memory with resistive networks. In 2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics: Advancing Circuits and Systems Innovation for Connected World, PrimeAsia 2017 - Proceedings (Vol. 2017-October, pp. 69-72). (Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics; Vol. 2017-October). IEEE Computer Society. https://doi.org/10.1109/PRIMEASIA.2017.8280366