On-chip measurements of standard-cell propagation delay

S. O. Churayev; B. T. Matkarimov; T. T. Paltashev

doi:10.1109/EWDTS.2010.5742113

On-chip measurements of standard-cell propagation delay

S. O. Churayev, B. T. Matkarimov, T. T. Paltashev

Biosensors and Bionstruments Laboratory

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

We report on implementation of random sampling methodology for on-chip measurements of the pin-to-pin propagation delay of single standard cells of core library. A test chip has been implemented in 0.13m GL130SB (130nm Logic Process) technology at Dongbu HiTek and used to monitor up to picosecond's timing behavior of 32 DUT's of core library. Observed mismatch between simulated and measured parameters helps to improve and verify library cell models.

Original language	English
Title of host publication	Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10
Pages	179-181
Number of pages	3
DOIs	https://doi.org/10.1109/EWDTS.2010.5742113
Publication status	Published - Dec 1 2010
Event	IEEE East-West Design and Test Symposium, EWDTS'10 - St. Petersburg, Russian Federation Duration: Sep 17 2010 → Sep 20 2010

Publication series

Name	Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10

Other

Other	IEEE East-West Design and Test Symposium, EWDTS'10
Country	Russian Federation
City	St. Petersburg
Period	9/17/10 → 9/20/10

ASJC Scopus subject areas

Computer Science Applications
Hardware and Architecture

Access to Document

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Churayev, SO, Matkarimov, BT & Paltashev, TT 2010, On-chip measurements of standard-cell propagation delay. in Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10., 5742113, Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10, pp. 179-181, IEEE East-West Design and Test Symposium, EWDTS'10, St. Petersburg, Russian Federation, 9/17/10. https://doi.org/10.1109/EWDTS.2010.5742113

@inproceedings{1186462f420246f3a0b331c27da22fdd,

title = "On-chip measurements of standard-cell propagation delay",

abstract = "We report on implementation of random sampling methodology for on-chip measurements of the pin-to-pin propagation delay of single standard cells of core library. A test chip has been implemented in 0.13m GL130SB (130nm Logic Process) technology at Dongbu HiTek and used to monitor up to picosecond's timing behavior of 32 DUT's of core library. Observed mismatch between simulated and measured parameters helps to improve and verify library cell models.",

author = "Churayev, {S. O.} and Matkarimov, {B. T.} and Paltashev, {T. T.}",

year = "2010",

month = dec,

day = "1",

doi = "10.1109/EWDTS.2010.5742113",

language = "English",

isbn = "9781424495566",

series = "Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10",

pages = "179--181",

booktitle = "Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10",

note = "IEEE East-West Design and Test Symposium, EWDTS'10 ; Conference date: 17-09-2010 Through 20-09-2010",

}

TY - GEN

T1 - On-chip measurements of standard-cell propagation delay

AU - Churayev, S. O.

AU - Matkarimov, B. T.

AU - Paltashev, T. T.

PY - 2010/12/1

Y1 - 2010/12/1

N2 - We report on implementation of random sampling methodology for on-chip measurements of the pin-to-pin propagation delay of single standard cells of core library. A test chip has been implemented in 0.13m GL130SB (130nm Logic Process) technology at Dongbu HiTek and used to monitor up to picosecond's timing behavior of 32 DUT's of core library. Observed mismatch between simulated and measured parameters helps to improve and verify library cell models.

AB - We report on implementation of random sampling methodology for on-chip measurements of the pin-to-pin propagation delay of single standard cells of core library. A test chip has been implemented in 0.13m GL130SB (130nm Logic Process) technology at Dongbu HiTek and used to monitor up to picosecond's timing behavior of 32 DUT's of core library. Observed mismatch between simulated and measured parameters helps to improve and verify library cell models.

UR - http://www.scopus.com/inward/record.url?scp=79955965108&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79955965108&partnerID=8YFLogxK

U2 - 10.1109/EWDTS.2010.5742113

DO - 10.1109/EWDTS.2010.5742113

M3 - Conference contribution

AN - SCOPUS:79955965108

SN - 9781424495566

T3 - Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10

SP - 179

EP - 181

BT - Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10

T2 - IEEE East-West Design and Test Symposium, EWDTS'10

Y2 - 17 September 2010 through 20 September 2010

ER -