TY - GEN
T1 - On-chip measurements of standard-cell propagation delay
AU - Churayev, S. O.
AU - Matkarimov, B. T.
AU - Paltashev, T. T.
PY - 2010/12/1
Y1 - 2010/12/1
N2 - We report on implementation of random sampling methodology for on-chip measurements of the pin-to-pin propagation delay of single standard cells of core library. A test chip has been implemented in 0.13m GL130SB (130nm Logic Process) technology at Dongbu HiTek and used to monitor up to picosecond's timing behavior of 32 DUT's of core library. Observed mismatch between simulated and measured parameters helps to improve and verify library cell models.
AB - We report on implementation of random sampling methodology for on-chip measurements of the pin-to-pin propagation delay of single standard cells of core library. A test chip has been implemented in 0.13m GL130SB (130nm Logic Process) technology at Dongbu HiTek and used to monitor up to picosecond's timing behavior of 32 DUT's of core library. Observed mismatch between simulated and measured parameters helps to improve and verify library cell models.
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U2 - 10.1109/EWDTS.2010.5742113
DO - 10.1109/EWDTS.2010.5742113
M3 - Conference contribution
AN - SCOPUS:79955965108
SN - 9781424495566
T3 - Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10
SP - 179
EP - 181
BT - Proceedings of IEEE East-West Design and Test Symposium, EWDTS'10
T2 - IEEE East-West Design and Test Symposium, EWDTS'10
Y2 - 17 September 2010 through 20 September 2010
ER -