On-chip measurements of standard-cell propagation delay

S. O. Churayev, B. T. Matkarimov, T. T. Paltashev

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

We report on implementation of random sampling methodology for on-chip measurements of the pin-to-pin propagation delay of single standard cells of core library. A test chip has been implemented in 0.13m GL130SB (130nm Logic Process) technology at Dongbu HiTek and used to monitor up to picosecond's timing behavior of 32 DUT's of core library. Observed mismatch between simulated and measured parameters helps to improve and verify library cell models.

Original languageEnglish
Title of host publicationProceedings of IEEE East-West Design and Test Symposium, EWDTS'10
Pages179-181
Number of pages3
DOIs
Publication statusPublished - Dec 1 2010
EventIEEE East-West Design and Test Symposium, EWDTS'10 - St. Petersburg, Russian Federation
Duration: Sep 17 2010Sep 20 2010

Publication series

NameProceedings of IEEE East-West Design and Test Symposium, EWDTS'10

Other

OtherIEEE East-West Design and Test Symposium, EWDTS'10
CountryRussian Federation
CitySt. Petersburg
Period9/17/109/20/10

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture

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