Optimized power and speed of Split-Radix, Radix-4 and Radix-2 FFT structures

Mahsa Shirzadian Gilan, Behrouz Maham

Research output: Contribution to journalArticlepeer-review

Abstract

Fast Fourier transform (FFT) is a fundamental building block for digital signal processing applications where high processing speed is crucial. Resource utilization in implementing FFT structures can be minimized by optimizing the performance of multipliers and adders used within the design. FFTs are also widely used in various machine learning algorithms. To achieve increased processor efficiency and reduced resource utilization, we propose a hardware design for Radix-2, Radix-4, and Split-Radix FFT architectures that utilizes a novel parallel prefix adder. This design offers lower power consumption, smaller chip area, and faster operation compared to existing architectures. Our performance analysis focuses on metrics such as power consumption, clock speed, and hardware complexity for Radix-2, Radix-4, and Split-Radix FFT algorithms implemented with the proposed adder. We compare these metrics using our proposed arithmetic structure against existing adder designs. The results indicate that the Split-Radix FFT architecture achieves lower power consumption and smaller chip area compared to Radix-4 and Radix-2 methods. Additionally, the Split-Radix FFT exhibits a higher clock speed. Therefore, based on these findings, the Split-Radix algorithm appears to be a compelling choice for implementation on field-programmable gate arrays due to its high speed and lower power consumption.

Original languageEnglish
Article number81
JournalEurasip Journal on Advances in Signal Processing
Volume2024
Issue number1
DOIs
Publication statusPublished - Dec 2024

Keywords

  • Parallel prefix adder
  • Power consumption
  • Radix-2
  • Radix-4
  • Speed
  • Split-Radix

ASJC Scopus subject areas

  • Signal Processing
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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