Programmable Memristive Threshold Logic Gate Array

Olga Krestinskaya; Akshay Kumar Maan; Alex James Pappachen

doi:10.1109/APCCAS.2018.8605646

Programmable Memristive Threshold Logic Gate Array

Olga Krestinskaya, Akshay Kumar Maan, Alex James Pappachen

Department of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC 180nm CMOS technology. The on-chip area and power dissipation of the simulated 3 × 4 TLG array is 1463μm ² and 425μW, respectively.

Original language	English
Title of host publication	2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	313-316
Number of pages	4
ISBN (Electronic)	9781538682401
DOIs	https://doi.org/10.1109/APCCAS.2018.8605646
Publication status	Published - Jan 8 2019
Event	14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 - Chengdu, China Duration: Oct 26 2018 → Oct 30 2018

Publication series

Name	2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018

Conference

Conference	14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
Country	China
City	Chengdu
Period	10/26/18 → 10/30/18

ASJC Scopus subject areas

Biomedical Engineering
Electrical and Electronic Engineering
Instrumentation

Access to Document

10.1109/APCCAS.2018.8605646

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Krestinskaya, O., Maan, A. K., & James Pappachen, A. (2019). Programmable Memristive Threshold Logic Gate Array. In 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 (pp. 313-316). [8605646] (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2018.8605646

Programmable Memristive Threshold Logic Gate Array. / Krestinskaya, Olga; Maan, Akshay Kumar; James Pappachen, Alex.

2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 313-316 8605646 (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Krestinskaya, O, Maan, AK & James Pappachen, A 2019, Programmable Memristive Threshold Logic Gate Array. in 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018., 8605646, 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Institute of Electrical and Electronics Engineers Inc., pp. 313-316, 14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, 10/26/18. https://doi.org/10.1109/APCCAS.2018.8605646

Krestinskaya O, Maan AK, James Pappachen A. Programmable Memristive Threshold Logic Gate Array. In 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 313-316. 8605646. (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018). https://doi.org/10.1109/APCCAS.2018.8605646

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