Abstract
This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC 180nm CMOS technology. The on-chip area and power dissipation of the simulated 3 × 4 TLG array is 1463μm 2 and 425μW, respectively.
| Original language | English |
|---|---|
| Title of host publication | 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 313-316 |
| Number of pages | 4 |
| ISBN (Electronic) | 9781538682401 |
| DOIs | |
| Publication status | Published - Jan 8 2019 |
| Event | 14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 - Chengdu, China Duration: Oct 26 2018 → Oct 30 2018 |
Publication series
| Name | 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 |
|---|
Conference
| Conference | 14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 |
|---|---|
| Country | China |
| City | Chengdu |
| Period | 10/26/18 → 10/30/18 |
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ASJC Scopus subject areas
- Biomedical Engineering
- Electrical and Electronic Engineering
- Instrumentation
Cite this
Programmable Memristive Threshold Logic Gate Array. / Krestinskaya, Olga; Maan, Akshay Kumar; James Pappachen, Alex.
2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 313-316 8605646 (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Programmable Memristive Threshold Logic Gate Array
AU - Krestinskaya, Olga
AU - Maan, Akshay Kumar
AU - James Pappachen, Alex
PY - 2019/1/8
Y1 - 2019/1/8
N2 - This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC 180nm CMOS technology. The on-chip area and power dissipation of the simulated 3 × 4 TLG array is 1463μm 2 and 425μW, respectively.
AB - This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC 180nm CMOS technology. The on-chip area and power dissipation of the simulated 3 × 4 TLG array is 1463μm 2 and 425μW, respectively.
UR - http://www.scopus.com/inward/record.url?scp=85062229906&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85062229906&partnerID=8YFLogxK
U2 - 10.1109/APCCAS.2018.8605646
DO - 10.1109/APCCAS.2018.8605646
M3 - Conference contribution
AN - SCOPUS:85062229906
T3 - 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
SP - 313
EP - 316
BT - 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
PB - Institute of Electrical and Electronics Engineers Inc.
ER -