Programmable Memristive Threshold Logic Gate Array

Olga Krestinskaya, Akshay Kumar Maan, Alex James Pappachen

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper proposes the implementation of programmable threshold logic gate (TLG) crossbar array based on modified TLG cells for high speed processing and computation. The proposed TLG array operation does not depend on input signal and time pulses, comparing to the existing architectures. The circuit is implemented using TSMC 180nm CMOS technology. The on-chip area and power dissipation of the simulated 3 × 4 TLG array is 1463μm 2 and 425μW, respectively.

Original languageEnglish
Title of host publication2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages313-316
Number of pages4
ISBN (Electronic)9781538682401
DOIs
Publication statusPublished - Jan 8 2019
Event14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 - Chengdu, China
Duration: Oct 26 2018Oct 30 2018

Publication series

Name2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018

Conference

Conference14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018
CountryChina
CityChengdu
Period10/26/1810/30/18

Fingerprint

threshold logic
Threshold logic
Logic gates
Energy dissipation
CMOS
dissipation
chips
high speed
Networks (circuits)
Processing
pulses
cells

ASJC Scopus subject areas

  • Biomedical Engineering
  • Electrical and Electronic Engineering
  • Instrumentation

Cite this

Krestinskaya, O., Maan, A. K., & James Pappachen, A. (2019). Programmable Memristive Threshold Logic Gate Array. In 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018 (pp. 313-316). [8605646] (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APCCAS.2018.8605646

Programmable Memristive Threshold Logic Gate Array. / Krestinskaya, Olga; Maan, Akshay Kumar; James Pappachen, Alex.

2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. p. 313-316 8605646 (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Krestinskaya, O, Maan, AK & James Pappachen, A 2019, Programmable Memristive Threshold Logic Gate Array. in 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018., 8605646, 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Institute of Electrical and Electronics Engineers Inc., pp. 313-316, 14th IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, 10/26/18. https://doi.org/10.1109/APCCAS.2018.8605646
Krestinskaya O, Maan AK, James Pappachen A. Programmable Memristive Threshold Logic Gate Array. In 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc. 2019. p. 313-316. 8605646. (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018). https://doi.org/10.1109/APCCAS.2018.8605646
Krestinskaya, Olga ; Maan, Akshay Kumar ; James Pappachen, Alex. / Programmable Memristive Threshold Logic Gate Array. 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018. Institute of Electrical and Electronics Engineers Inc., 2019. pp. 313-316 (2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018).
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