Reconfigurable Threshold Logic Networks in FPGA for Moving Object Detection

Threshold logic inspires from the principle of the firing of neurons mimicking synaptic connections of a binary neural network to create generalized logical functions for solving complex cognitive tasks such as object detection. We propose an implementation of modular and hierarchical threshold logic network in FPGA that aims to provide a low complexity near-sensor co-processing hardware solution for object detection in digital cameras. The proposed network has been designed and implemented on a Xilinx Zynq SoC. The solution is robust in terms of object detection even in the presence of high levels of occlusion, noise and illumination changes. The total power consumption of the design is estimated to be 8.6 W. Performance analysis of the detector IP core is thoroughly simulated on test databases for computer vision with real-world images. The object detection module ensures a high performance rate of about 5000 frames per second at 100 MHz clock frequency while processing 100 × 100 pixel images.