TY - GEN

T1 - Synthesis of small reversible and pseudo-reversible circuits using Y-gates and inverse Y-gates

AU - Perkowski, Marek

AU - Alhagi, Nouraddin

AU - Lukac, Martin

AU - Saxena, Neha

AU - Blakely, Scott

PY - 2010/8/12

Y1 - 2010/8/12

N2 - This paper presents synthesis of reversible circuits using the Y-gate. The standard reversible circuit has the same number of input and output signals. Such circuits are in general built from reversible gates that similarly have the same number of inputs and outputs. In new technologies, the Y-gate has unequal number of inputs and outputs and so the circuit composed of such gates can have either equal (standard model) or unequal numbers of input and output signals. We introduce the concepts of pseudo-reversible functions. First, a brief overview of reversible logic, Y-gates and Prolog, which form the foundation for this work, is presented. This is followed by the description of an exhaustive search algorithm that generates all circuits from Y gates under certain constraints. We give examples of synthesized circuits.

AB - This paper presents synthesis of reversible circuits using the Y-gate. The standard reversible circuit has the same number of input and output signals. Such circuits are in general built from reversible gates that similarly have the same number of inputs and outputs. In new technologies, the Y-gate has unequal number of inputs and outputs and so the circuit composed of such gates can have either equal (standard model) or unequal numbers of input and output signals. We introduce the concepts of pseudo-reversible functions. First, a brief overview of reversible logic, Y-gates and Prolog, which form the foundation for this work, is presented. This is followed by the description of an exhaustive search algorithm that generates all circuits from Y gates under certain constraints. We give examples of synthesized circuits.

UR - http://www.scopus.com/inward/record.url?scp=77955325952&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77955325952&partnerID=8YFLogxK

U2 - 10.1109/ISMVL.2010.53

DO - 10.1109/ISMVL.2010.53

M3 - Conference contribution

AN - SCOPUS:77955325952

SN - 9780769540245

T3 - Proceedings of The International Symposium on Multiple-Valued Logic

SP - 245

EP - 251

BT - ISMVL 2010 - 40th IEEE International Symposium on Multiple-Valued Logic

T2 - 40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010

Y2 - 26 May 2010 through 28 May 2010

ER -