### Abstract

This paper presents synthesis of reversible circuits using the Y-gate. The standard reversible circuit has the same number of input and output signals. Such circuits are in general built from reversible gates that similarly have the same number of inputs and outputs. In new technologies, the Y-gate has unequal number of inputs and outputs and so the circuit composed of such gates can have either equal (standard model) or unequal numbers of input and output signals. We introduce the concepts of pseudo-reversible functions. First, a brief overview of reversible logic, Y-gates and Prolog, which form the foundation for this work, is presented. This is followed by the description of an exhaustive search algorithm that generates all circuits from Y gates under certain constraints. We give examples of synthesized circuits.

Original language | English |
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Title of host publication | ISMVL 2010 - 40th IEEE International Symposium on Multiple-Valued Logic |

Pages | 245-251 |

Number of pages | 7 |

DOIs | |

Publication status | Published - Aug 12 2010 |

Event | 40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010 - Barcelona, Spain Duration: May 26 2010 → May 28 2010 |

### Publication series

Name | Proceedings of The International Symposium on Multiple-Valued Logic |
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ISSN (Print) | 0195-623X |

### Other

Other | 40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010 |
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Country | Spain |

City | Barcelona |

Period | 5/26/10 → 5/28/10 |

### ASJC Scopus subject areas

- Computer Science(all)
- Mathematics(all)

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## Cite this

*ISMVL 2010 - 40th IEEE International Symposium on Multiple-Valued Logic*(pp. 245-251). [5489143] (Proceedings of The International Symposium on Multiple-Valued Logic). https://doi.org/10.1109/ISMVL.2010.53