Abstract
This paper presents synthesis of reversible circuits using the Y-gate. The standard reversible circuit has the same number of input and output signals. Such circuits are in general built from reversible gates that similarly have the same number of inputs and outputs. In new technologies, the Y-gate has unequal number of inputs and outputs and so the circuit composed of such gates can have either equal (standard model) or unequal numbers of input and output signals. We introduce the concepts of pseudo-reversible functions. First, a brief overview of reversible logic, Y-gates and Prolog, which form the foundation for this work, is presented. This is followed by the description of an exhaustive search algorithm that generates all circuits from Y gates under certain constraints. We give examples of synthesized circuits.
| Original language | English |
|---|---|
| Title of host publication | Proceedings of The International Symposium on Multiple-Valued Logic |
| Pages | 245-251 |
| Number of pages | 7 |
| DOIs | |
| Publication status | Published - 2010 |
| Externally published | Yes |
| Event | 40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010 - Barcelona, Spain Duration: May 26 2010 → May 28 2010 |
Other
| Other | 40th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2010 |
|---|---|
| Country | Spain |
| City | Barcelona |
| Period | 5/26/10 → 5/28/10 |
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ASJC Scopus subject areas
- Computer Science(all)
- Mathematics(all)
Cite this
Synthesis of small reversible and pseudo-reversible circuits using Y-gates and inverse Y-gates. / Perkowski, Marek; Alhagi, Nouraddin; Lukac, Martin; Saxena, Neha; Blakely, Scott.
Proceedings of The International Symposium on Multiple-Valued Logic. 2010. p. 245-251 5489143.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
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TY - GEN
T1 - Synthesis of small reversible and pseudo-reversible circuits using Y-gates and inverse Y-gates
AU - Perkowski, Marek
AU - Alhagi, Nouraddin
AU - Lukac, Martin
AU - Saxena, Neha
AU - Blakely, Scott
PY - 2010
Y1 - 2010
N2 - This paper presents synthesis of reversible circuits using the Y-gate. The standard reversible circuit has the same number of input and output signals. Such circuits are in general built from reversible gates that similarly have the same number of inputs and outputs. In new technologies, the Y-gate has unequal number of inputs and outputs and so the circuit composed of such gates can have either equal (standard model) or unequal numbers of input and output signals. We introduce the concepts of pseudo-reversible functions. First, a brief overview of reversible logic, Y-gates and Prolog, which form the foundation for this work, is presented. This is followed by the description of an exhaustive search algorithm that generates all circuits from Y gates under certain constraints. We give examples of synthesized circuits.
AB - This paper presents synthesis of reversible circuits using the Y-gate. The standard reversible circuit has the same number of input and output signals. Such circuits are in general built from reversible gates that similarly have the same number of inputs and outputs. In new technologies, the Y-gate has unequal number of inputs and outputs and so the circuit composed of such gates can have either equal (standard model) or unequal numbers of input and output signals. We introduce the concepts of pseudo-reversible functions. First, a brief overview of reversible logic, Y-gates and Prolog, which form the foundation for this work, is presented. This is followed by the description of an exhaustive search algorithm that generates all circuits from Y gates under certain constraints. We give examples of synthesized circuits.
UR - http://www.scopus.com/inward/record.url?scp=77955325952&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=77955325952&partnerID=8YFLogxK
U2 - 10.1109/ISMVL.2010.53
DO - 10.1109/ISMVL.2010.53
M3 - Conference contribution
AN - SCOPUS:77955325952
SN - 9780769540245
SP - 245
EP - 251
BT - Proceedings of The International Symposium on Multiple-Valued Logic
ER -