The impact of InAlAs spacer layer on DC characteristics of InP/InAlAs/GaAsSb/InP DHBTs

S. W. Cho, M. S. Park, T. W. Kim, J. H. Jang, I. Adesida, N. Pan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

GaAsSb-based double heterojunction bipolar transistors (DHBTs) were fabricated and their dc performances were characterized. The device heterostructures in this study incorporated thin InAlAs spacer layer between GaAsSb base layer and InP emitter layer. The impact of the thin InALAs spacer layer on the dc performance of GaAsSb-based DHBTs were investigated by comparing the dc characteristics of devices fabricated on InP/InALAs/GaAsSb/InP and conventional InP/ GaAsSb/InP heterostructures.

Original languageEnglish
Title of host publication2005 International Semiconductor Device Research Symposium
Pages394-395
Number of pages2
Publication statusPublished - Dec 1 2005
Event2005 International Semiconductor Device Research Symposium - Bethesda, MD, United States
Duration: Dec 7 2005Dec 9 2005

Publication series

Name2005 International Semiconductor Device Research Symposium
Volume2005

Other

Other2005 International Semiconductor Device Research Symposium
CountryUnited States
CityBethesda, MD
Period12/7/0512/9/05

ASJC Scopus subject areas

  • Engineering(all)

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