The impact of InAlAs spacer layer on DC characteristics of InP/InAlAs/GaAsSb/InP DHBTs

S. W. Cho, M. S. Park, T. W. Kim, J. H. Jang, I. Adesida, N. Pan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

GaAsSb-based double heterojunction bipolar transistors (DHBTs) were fabricated and their dc performances were characterized. The device heterostructures in this study incorporated thin InAlAs spacer layer between GaAsSb base layer and InP emitter layer. The impact of the thin InALAs spacer layer on the dc performance of GaAsSb-based DHBTs were investigated by comparing the dc characteristics of devices fabricated on InP/InALAs/GaAsSb/InP and conventional InP/ GaAsSb/InP heterostructures.

Original languageEnglish
Title of host publication2005 International Semiconductor Device Research Symposium
Pages394-395
Number of pages2
Volume2005
Publication statusPublished - 2005
Externally publishedYes
Event2005 International Semiconductor Device Research Symposium - Bethesda, MD, United States
Duration: Dec 7 2005Dec 9 2005

Other

Other2005 International Semiconductor Device Research Symposium
CountryUnited States
CityBethesda, MD
Period12/7/0512/9/05

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Heterojunction bipolar transistors
Heterojunctions

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Cho, S. W., Park, M. S., Kim, T. W., Jang, J. H., Adesida, I., & Pan, N. (2005). The impact of InAlAs spacer layer on DC characteristics of InP/InAlAs/GaAsSb/InP DHBTs. In 2005 International Semiconductor Device Research Symposium (Vol. 2005, pp. 394-395). [1596152]

The impact of InAlAs spacer layer on DC characteristics of InP/InAlAs/GaAsSb/InP DHBTs. / Cho, S. W.; Park, M. S.; Kim, T. W.; Jang, J. H.; Adesida, I.; Pan, N.

2005 International Semiconductor Device Research Symposium. Vol. 2005 2005. p. 394-395 1596152.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Cho, SW, Park, MS, Kim, TW, Jang, JH, Adesida, I & Pan, N 2005, The impact of InAlAs spacer layer on DC characteristics of InP/InAlAs/GaAsSb/InP DHBTs. in 2005 International Semiconductor Device Research Symposium. vol. 2005, 1596152, pp. 394-395, 2005 International Semiconductor Device Research Symposium, Bethesda, MD, United States, 12/7/05.
Cho SW, Park MS, Kim TW, Jang JH, Adesida I, Pan N. The impact of InAlAs spacer layer on DC characteristics of InP/InAlAs/GaAsSb/InP DHBTs. In 2005 International Semiconductor Device Research Symposium. Vol. 2005. 2005. p. 394-395. 1596152
Cho, S. W. ; Park, M. S. ; Kim, T. W. ; Jang, J. H. ; Adesida, I. ; Pan, N. / The impact of InAlAs spacer layer on DC characteristics of InP/InAlAs/GaAsSb/InP DHBTs. 2005 International Semiconductor Device Research Symposium. Vol. 2005 2005. pp. 394-395
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AB - GaAsSb-based double heterojunction bipolar transistors (DHBTs) were fabricated and their dc performances were characterized. The device heterostructures in this study incorporated thin InAlAs spacer layer between GaAsSb base layer and InP emitter layer. The impact of the thin InALAs spacer layer on the dc performance of GaAsSb-based DHBTs were investigated by comparing the dc characteristics of devices fabricated on InP/InALAs/GaAsSb/InP and conventional InP/ GaAsSb/InP heterostructures.

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