Two-to -one multiplexer using pseudoresistive load

Asha Anju; S. Gowri; M. R. Baiju; K. R. Ajayan; A. P. James

Two-to -one multiplexer using pseudoresistive load

Asha Anju, S. Gowri, M. R. Baiju, K. R. Ajayan, A. P. James

Department of Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper analyses a two-to-one multiplexer that uses pseudoresistive load realized using NMOS or PMOS transistors in the pull down path. MOS as a pseudoresistor is studied. The variation of the output rise time, fall time and voltage swing with the load pseudoresistance is studied and mathematically analyzed. NMOS and PMOS loads are compared in terms of their performances. The simulations are done using SPICE3F5 utilizing the BSIM 3v3 models of MOSFET.

Original language	English
Publication status	Published - Jan 1 2006
Event	MIPRO 2006 - 29th International Convention: Microelectronics, Electronics and Electronic Technologies, MEET, Hypermedia and Grid Systems HGS - Opatija, Croatia Duration: May 22 2006 → May 26 2006

Other

Other	MIPRO 2006 - 29th International Convention: Microelectronics, Electronics and Electronic Technologies, MEET, Hypermedia and Grid Systems HGS
Country	Croatia
City	Opatija
Period	5/22/06 → 5/26/06

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials
Surfaces, Coatings and Films
Condensed Matter Physics
Atomic and Molecular Physics, and Optics

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Two-to -one multiplexer using pseudoresistive load. / Anju, Asha; Gowri, S.; Baiju, M. R.; Ajayan, K. R.; James, A. P.

2006. Paper presented at MIPRO 2006 - 29th International Convention: Microelectronics, Electronics and Electronic Technologies, MEET, Hypermedia and Grid Systems HGS, Opatija, Croatia.

Research output: Contribution to conference › Paper › peer-review

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AU - Gowri, S.

AU - Baiju, M. R.

AU - Ajayan, K. R.

AU - James, A. P.

PY - 2006/1/1

Y1 - 2006/1/1

N2 - This paper analyses a two-to-one multiplexer that uses pseudoresistive load realized using NMOS or PMOS transistors in the pull down path. MOS as a pseudoresistor is studied. The variation of the output rise time, fall time and voltage swing with the load pseudoresistance is studied and mathematically analyzed. NMOS and PMOS loads are compared in terms of their performances. The simulations are done using SPICE3F5 utilizing the BSIM 3v3 models of MOSFET.

AB - This paper analyses a two-to-one multiplexer that uses pseudoresistive load realized using NMOS or PMOS transistors in the pull down path. MOS as a pseudoresistor is studied. The variation of the output rise time, fall time and voltage swing with the load pseudoresistance is studied and mathematically analyzed. NMOS and PMOS loads are compared in terms of their performances. The simulations are done using SPICE3F5 utilizing the BSIM 3v3 models of MOSFET.

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T2 - MIPRO 2006 - 29th International Convention: Microelectronics, Electronics and Electronic Technologies, MEET, Hypermedia and Grid Systems HGS

Y2 - 22 May 2006 through 26 May 2006

ER -

Two-to -one multiplexer using pseudoresistive load

Abstract

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ASJC Scopus subject areas

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