Two-to -one multiplexer using pseudoresistive load

Asha Anju, S. Gowri, M. R. Baiju, K. R. Ajayan, A. P. James

Research output: Contribution to conferencePaperpeer-review

Abstract

This paper analyses a two-to-one multiplexer that uses pseudoresistive load realized using NMOS or PMOS transistors in the pull down path. MOS as a pseudoresistor is studied. The variation of the output rise time, fall time and voltage swing with the load pseudoresistance is studied and mathematically analyzed. NMOS and PMOS loads are compared in terms of their performances. The simulations are done using SPICE3F5 utilizing the BSIM 3v3 models of MOSFET.

Original languageEnglish
Publication statusPublished - Jan 1 2006
EventMIPRO 2006 - 29th International Convention: Microelectronics, Electronics and Electronic Technologies, MEET, Hypermedia and Grid Systems HGS - Opatija, Croatia
Duration: May 22 2006May 26 2006

Other

OtherMIPRO 2006 - 29th International Convention: Microelectronics, Electronics and Electronic Technologies, MEET, Hypermedia and Grid Systems HGS
CountryCroatia
CityOpatija
Period5/22/065/26/06

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Surfaces, Coatings and Films
  • Condensed Matter Physics
  • Atomic and Molecular Physics, and Optics

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