TY - GEN
T1 - VLSI platform for real-world intelligent integrated systems based on algorithm selection
AU - Lukac, Martin
AU - Kameyama, Michitaka
AU - Fujioka, Yoshichika
PY - 2013/10/25
Y1 - 2013/10/25
N2 - A real-world intelligent system consists of three basic modules: environment recognition, prediction (or estimation), and behavior planning. To obtain high quality results in these modules, high speed processing and real time adaptability on a case by case basis are required. In each of the above mentioned modules, many different algorithms and algorithms networks exists and provide various performances on a case by case basis. Thus, a mechanism that for any of the three computational stages selects the best possible algorithm is required. We propose a platform based on the algorithm selection approach to the problem of natural image understanding. This selection mechanism is based on machine learning; a bottom-up algorithm selection from real-world image features and a top-down algorithm selection using information obtained from a high level symbolic world description and algorithm suitability. To accommodate the highspeed processing requirements, the high-frequency of real-time reconfiguration and a low-cost of implementation, we are using present a novel dynamic reconfigurable VLSI processor for real-time adaptation of the algorithm selection. The new architecture includes a fine-grain Digital Reconfigurable Processor, a distributed configuration memory to solve the data transfer bottleneck and an intra-chip packet routing scheme to reduce the size of the configuration memory.
AB - A real-world intelligent system consists of three basic modules: environment recognition, prediction (or estimation), and behavior planning. To obtain high quality results in these modules, high speed processing and real time adaptability on a case by case basis are required. In each of the above mentioned modules, many different algorithms and algorithms networks exists and provide various performances on a case by case basis. Thus, a mechanism that for any of the three computational stages selects the best possible algorithm is required. We propose a platform based on the algorithm selection approach to the problem of natural image understanding. This selection mechanism is based on machine learning; a bottom-up algorithm selection from real-world image features and a top-down algorithm selection using information obtained from a high level symbolic world description and algorithm suitability. To accommodate the highspeed processing requirements, the high-frequency of real-time reconfiguration and a low-cost of implementation, we are using present a novel dynamic reconfigurable VLSI processor for real-time adaptation of the algorithm selection. The new architecture includes a fine-grain Digital Reconfigurable Processor, a distributed configuration memory to solve the data transfer bottleneck and an intra-chip packet routing scheme to reduce the size of the configuration memory.
KW - Algorithm selection
KW - Memory reduction
KW - Natural image processing
KW - Reconfigurable VLSI
UR - http://www.scopus.com/inward/record.url?scp=84886903365&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84886903365&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:84886903365
SN - 9789728939946
T3 - Proc. of the IADIS Int. Conf. Information Systems Post-Implementation and Change Management 2013, ISPCM 2013, Proc. of the IADIS Int. Conf. Theory and Practice in Modern Computing 2013, TPMC 2013
SP - 27
EP - 34
BT - Proc. of the IADIS Int. Conf. Information Systems Post-Implementation and Change Management 2013, ISPCM 2013, Proc. of the IADIS Int. Conf. Theory and Practice in Modern Computing 2013, TPMC 2013
T2 - IADIS International Conference Information Systems Post-Implementation and Change Management 2013, ISPCM 2013, IADIS International Conference TPMC 2013, Part of the IADIS Multi Conference on Computer Science and Information Systems 2013, MCCSIS 2013
Y2 - 22 July 2013 through 24 July 2013
ER -