Zycap: Efficient partial reconfiguration management on the xilinx zynq

Kizheppatt Vipin, Suhaib A. Fahmy

Research output: Contribution to journalArticlepeer-review

66 Citations (Scopus)

Abstract

New hybrid FPGA platforms that couple processors with a reconfigurable fabric, such as the Xilinx Zynq, offer an alternative view of reconfigurable computing where software applications leverage hardware resources through the use of often reconfigured accelerators. For this to be feasible, reconfiguration overheads must be reduced so that the processor is not burdened with managing the process. We discuss partial reconfiguration (PR) on these architectures, and present an open source controller, ZyCAP, that overcomes the limitations of existing methods, offering more effective use of hardware resources in such architectures. ZyCAP combines high-throughput configuration with a high-level software interface that frees the processor from detailed PR management, making PR on the Zynq easy and efficient.

Original languageEnglish
Article number6780588
Pages (from-to)41-44
Number of pages4
JournalIEEE Embedded Systems Letters
Volume6
Issue number3
DOIs
Publication statusPublished - 2014
Externally publishedYes

Keywords

  • Accelerator architectures
  • Field-programmable gate arrays (fpgas)
  • Reconfigurable computing

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Computer Science(all)

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