Zycap: Efficient partial reconfiguration management on the xilinx zynq

Kizheppatt Vipin, Suhaib A. Fahmy

Research output: Contribution to journalArticle

51 Citations (Scopus)

Abstract

New hybrid FPGA platforms that couple processors with a reconfigurable fabric, such as the Xilinx Zynq, offer an alternative view of reconfigurable computing where software applications leverage hardware resources through the use of often reconfigured accelerators. For this to be feasible, reconfiguration overheads must be reduced so that the processor is not burdened with managing the process. We discuss partial reconfiguration (PR) on these architectures, and present an open source controller, ZyCAP, that overcomes the limitations of existing methods, offering more effective use of hardware resources in such architectures. ZyCAP combines high-throughput configuration with a high-level software interface that frees the processor from detailed PR management, making PR on the Zynq easy and efficient.

Original languageEnglish
Article number6780588
Pages (from-to)41-44
Number of pages4
JournalIEEE Embedded Systems Letters
Volume6
Issue number3
DOIs
Publication statusPublished - 2014
Externally publishedYes

Fingerprint

Application programs
Computer hardware
Particle accelerators
Field programmable gate arrays (FPGA)
Throughput
Hardware
Controllers

Keywords

  • Accelerator architectures
  • Field-programmable gate arrays (fpgas)
  • Reconfigurable computing

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Computer Science(all)

Cite this

Zycap : Efficient partial reconfiguration management on the xilinx zynq. / Vipin, Kizheppatt; Fahmy, Suhaib A.

In: IEEE Embedded Systems Letters, Vol. 6, No. 3, 6780588, 2014, p. 41-44.

Research output: Contribution to journalArticle

@article{7b587aff77074e349c78af67b3a91193,
title = "Zycap: Efficient partial reconfiguration management on the xilinx zynq",
abstract = "New hybrid FPGA platforms that couple processors with a reconfigurable fabric, such as the Xilinx Zynq, offer an alternative view of reconfigurable computing where software applications leverage hardware resources through the use of often reconfigured accelerators. For this to be feasible, reconfiguration overheads must be reduced so that the processor is not burdened with managing the process. We discuss partial reconfiguration (PR) on these architectures, and present an open source controller, ZyCAP, that overcomes the limitations of existing methods, offering more effective use of hardware resources in such architectures. ZyCAP combines high-throughput configuration with a high-level software interface that frees the processor from detailed PR management, making PR on the Zynq easy and efficient.",
keywords = "Accelerator architectures, Field-programmable gate arrays (fpgas), Reconfigurable computing",
author = "Kizheppatt Vipin and Fahmy, {Suhaib A.}",
year = "2014",
doi = "10.1109/LES.2014.2314390",
language = "English",
volume = "6",
pages = "41--44",
journal = "IEEE Embedded Systems Letters",
issn = "1943-0663",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

TY - JOUR

T1 - Zycap

T2 - Efficient partial reconfiguration management on the xilinx zynq

AU - Vipin, Kizheppatt

AU - Fahmy, Suhaib A.

PY - 2014

Y1 - 2014

N2 - New hybrid FPGA platforms that couple processors with a reconfigurable fabric, such as the Xilinx Zynq, offer an alternative view of reconfigurable computing where software applications leverage hardware resources through the use of often reconfigured accelerators. For this to be feasible, reconfiguration overheads must be reduced so that the processor is not burdened with managing the process. We discuss partial reconfiguration (PR) on these architectures, and present an open source controller, ZyCAP, that overcomes the limitations of existing methods, offering more effective use of hardware resources in such architectures. ZyCAP combines high-throughput configuration with a high-level software interface that frees the processor from detailed PR management, making PR on the Zynq easy and efficient.

AB - New hybrid FPGA platforms that couple processors with a reconfigurable fabric, such as the Xilinx Zynq, offer an alternative view of reconfigurable computing where software applications leverage hardware resources through the use of often reconfigured accelerators. For this to be feasible, reconfiguration overheads must be reduced so that the processor is not burdened with managing the process. We discuss partial reconfiguration (PR) on these architectures, and present an open source controller, ZyCAP, that overcomes the limitations of existing methods, offering more effective use of hardware resources in such architectures. ZyCAP combines high-throughput configuration with a high-level software interface that frees the processor from detailed PR management, making PR on the Zynq easy and efficient.

KW - Accelerator architectures

KW - Field-programmable gate arrays (fpgas)

KW - Reconfigurable computing

UR - http://www.scopus.com/inward/record.url?scp=84906840605&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84906840605&partnerID=8YFLogxK

U2 - 10.1109/LES.2014.2314390

DO - 10.1109/LES.2014.2314390

M3 - Article

VL - 6

SP - 41

EP - 44

JO - IEEE Embedded Systems Letters

JF - IEEE Embedded Systems Letters

SN - 1943-0663

IS - 3

M1 - 6780588

ER -