Bit-serial multiplier for FPGA applications

INIS

• applications 100%
• comparative evaluations 100%
• operation 100%
• topology 100%
• width 100%
• performance 50%
• implementation 50%
• calculation methods 50%
• input-output 50%
• ports 50%
• cost benefit analysis 50%

Keyphrases

• Bit-parallel multiplier 100%
• Field Programmable Gate Array 100%
• Bit-width 66%
• Computing Systems 33%
• Input-output 33%
• Cost-benefit 33%
• Output Port 33%
• Field Programmable Gate Array Implementation 33%
• Computation Cost 33%
• Multiplication Operation 33%
• Bit-serial 33%
• Performance Benefits 33%
• Binary multiplication 33%
• General Purpose Processor 33%
• Small Footprint 33%
• Computational Performance 33%

Computer Science

• Field Programmable Gate Array 100%
• Topology 50%
• Input/Output 25%
• General Purpose Processor 25%
• Multiplication Operation 25%